公开(公告)号：US20240031140A1

公开(公告)日：2024-01-25

申请号：US17814448

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： ANDREA BASSO ,  DUMITRU-DANIEL DINU ,  SANTOSH GHOSH ,  MANOJ SASTRY

IPC: H04L9/08 ,  H04L9/30

CPC classification number: H04L9/0858 ,  H04L9/3093 ,  H04L9/0869

Abstract: In one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication operation using the first input in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation, a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation, a third mode in which a masking or splitting side-channel protection is provided to the polynomial multiplication operation, or a fourth mode in which a masking and shuffling based side-channel protection is provided to the polynomial multiplication operation. Other examples may be described.

公开(公告)号：US20240031127A1

公开(公告)日：2024-01-25

申请号：US17814460

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： ANDREA BASSO ,  DUMITRU-DANIEL DINU ,  SANTOSH GHOSH ,  MANOJ SASTRY

IPC: H04L9/00 ,  H04L9/32 ,  H04L9/08 ,  H04L9/30

CPC classification number: H04L9/002 ,  H04L9/3247 ,  H04L9/0869 ,  H04L9/3093

Abstract: In one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication function using the first input as an element of a digital signature protocol, the polynomial multiplication function comprising a plurality of polynomial multiplication operations, the polynomial multiplication function performed in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation or a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation. Other examples may be described.