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公开(公告)号：US20230017447A1
公开(公告)日：2023-01-19
申请号：US17934682
申请日：2022-09-23
Applicant: Intel Corporation
Inventor： SANU MATHEW , MANOJ SASTRY , SANTOSH GHOSH , VIKRAM SURESH , ANDREW H. REINDERS , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.
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公开(公告)号：US20200162901A1
公开(公告)日：2020-05-21
申请号：US16707544
申请日：2019-12-09
Applicant: INTEL CORPORATION
Inventor： XIRUO LIU , SHABBIR AHMED , RALF GRAEFE , CHRISTOPHER GUTIERREZ , MARCIO JULIATO , RAFAEL ROSALES , MANOJ SASTRY , LIUYANG YANG
Abstract: Various embodiments are generally directed to techniques for providing improved privacy protection against vehicle tracking for connected vehicles of a vehicular network. For example, at least one road side unit may: identify a set of vehicles that require pseudonym changes and send an invitation for a pseudonym change event to each of the vehicles, determine at least a total number of the acceptances, determine whether the total number meets or exceeds a predetermined threshold number, send acknowledgement messages to the accepting vehicles if the threshold number is met, and form a vehicle group to coordinate the pseudonym change event during a privacy period. During the privacy period, the RSU and the vehicles may communicate with each other in a confidential and private manner via key-session-based unicast transmission, and coordinate transmission power and vehicle trajectory adjustments to maximize the benefits for safety and obfuscation for privacy.
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公开(公告)号：US20190319797A1
公开(公告)日：2019-10-17
申请号：US16455908
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： VIKRAM SURESH , SANU MATHEW , MANOJ SASTRY , SANTOSH GHOSH , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.
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公开(公告)号：US20220239498A1
公开(公告)日：2022-07-28
申请号：US17721656
申请日：2022-04-15
Applicant: Intel Corporation
Inventor： MANOJ SASTRY , RAFAEL MISOCZKI
Abstract: In one example an apparatus comprises a computer readable memory; and a signature module to generate a set of cryptographic keys for attestation of group member devices and a set of leaf nodes in a sub-tree of a Merkle tree corresponding to the set of cryptographic keys, forward the set of leaf nodes to a group manager device, receive, from the group manager device, a subset of intermediate nodes in the Merkle tree, the intermediate nodes being common to all available authentications paths through the Merkel tree for signatures originating in the sub-tree, and determine a cryptographic key that defines an authentication path through the Merkle tree, the authentication path comprising one or more nodes from the set of leaf nodes and one or more nodes from the intermediate nodes received from the group manager device. Other examples may be described.
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5.发明申请公开(公告)号：US20190319804A1
公开(公告)日：2019-10-17
申请号：US16456187
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： SANU MATHEW , MANOJ SASTRY , SANTOSH GHOSH , VIKRAM SURESH , ANDREW H. REINDERS , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.
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Patent Agency Ranking
公开(公告)号：US20190319803A1
公开(公告)日：2019-10-17
申请号：US16456064
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： RAFAEL MISOCZKI , VIKRAM SURESH , SANTOSH GHOSH , MANOJ SASTRY , SANU MATHEW , RAGHAVAN KUMAR
Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.
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公开(公告)号：US20220337421A1
公开(公告)日：2022-10-20
申请号：US17854911
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： SANTOSH GHOSH , VIKRAM SURESH , SANU MATHEW , MANOJ SASTRY , ANDREW H. REINDERS , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
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公开(公告)号：US20220272542A1
公开(公告)日：2022-08-25
申请号：US17742890
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： LIUYANG YANG , XIRUO LIU , MANOJ SASTRY , MARCIO JULIATO , SHABBIR AHMED , CHRISTOPHER GUTIERREZ
IPC: H04W12/122 , G06F13/40 , H04W12/00
Abstract: Systems, apparatus, methods, and techniques for reporting an attack or intrusion into an in-vehicle network are provided. The attack can be broadcast to connected vehicles over a vehicle-to-vehicle network. The broadcast can include an indication of a sub-system involved in the attack and can include a request for assistance in recovering from the attack. Connected vehicles can broadcast responses over the vehicle-to-vehicle network. The responses can include indications of data related to the compromised sub-system. The vehicle can receive the responses and can use the responses to recover from the attack, such as, estimate data.
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公开(公告)号：US20220086010A1
公开(公告)日：2022-03-17
申请号：US17534158
申请日：2021-11-23
Applicant: Intel Corporation
Inventor： VIKRAM SURESH , SANU MATHEW , MANOJ SASTRY , SANTOSH GHOSH , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.
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10.发明公开公开(公告)号：US20240031140A1
公开(公告)日：2024-01-25
申请号：US17814448
申请日：2022-07-22
Applicant: Intel Corporation
Inventor： ANDREA BASSO , DUMITRU-DANIEL DINU , SANTOSH GHOSH , MANOJ SASTRY
CPC classification number: H04L9/0858 , H04L9/3093 , H04L9/0869
Abstract: In one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication operation using the first input in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation, a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation, a third mode in which a masking or splitting side-channel protection is provided to the polynomial multiplication operation, or a fourth mode in which a masking and shuffling based side-channel protection is provided to the polynomial multiplication operation. Other examples may be described.
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