公开(公告)号：US20200044987A1

公开(公告)日：2020-02-06

申请号：US16577406

申请日：2019-09-20

Applicant: INTEL CORPORATION

Inventor： ELIEZER TAMIR ,  JESSE C. BRANDEBURG ,  ANIL VASUDEVAN

IPC: H04L12/861 ,  H04L12/879 ,  G06F9/52 ,  G06F9/48

Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US20170118143A1

公开(公告)日：2017-04-27

申请号：US15400629

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： ELIEZER TAMIR ,  JESSE C. BRANDEBURG ,  ANIL VASUDEVAN

IPC: H04L12/879 ,  G06F9/48 ,  G06F9/52

CPC classification number: H04L49/90 ,  G06F9/327 ,  G06F9/4498 ,  G06F9/4812 ,  G06F9/526 ,  H04L49/901

Abstract: Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US20170272370A1

公开(公告)日：2017-09-21

申请号：US15614455

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： ILANGO GANGA ,  ALAIN GRAVEL ,  THOMAS D. LOVETT ,  RADIA PERLMAN ,  GREG REGNIER ,  ANIL VASUDEVAN ,  HUGH WILKINSON

IPC: H04L12/851

CPC classification number: H04L47/2441 ,  Y02D30/30 ,  Y02D30/32

Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.