公开(公告)号：US20180143846A1

公开(公告)日：2018-05-24

申请号：US15874266

申请日：2018-01-18

Applicant: Intel Corporation

Inventor： STEPHEN T. PALERMO ,  SCOTT P. DUBAL ,  TREVOR COOPER ,  ANJALI S. JAIN ,  IOSIF GASPARAKIS ,  JR-SHIAN TSAI ,  MIKE BURSELL ,  PRADEEPSUNDER GANESH ,  PARTHASARATHY SARANGAM ,  JESSE C. BRANDEBURG

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/5011 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a “super” virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.

公开(公告)号：US20200044987A1

公开(公告)日：2020-02-06

申请号：US16577406

申请日：2019-09-20

Applicant: INTEL CORPORATION

Inventor： ELIEZER TAMIR ,  JESSE C. BRANDEBURG ,  ANIL VASUDEVAN

IPC: H04L12/861 ,  H04L12/879 ,  G06F9/52 ,  G06F9/48

Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US20170212776A1

公开(公告)日：2017-07-27

申请号：US15006320

申请日：2016-01-26

Applicant: Intel Corporation

Inventor： STEPHEN T. PALERMO ,  SCOTT P. DUBAL ,  TREVOR COOPER ,  ANJALI S. JAIN ,  IOSIF GASPARAKIS ,  JR-SHIAN TSAI ,  MIKE BURSELL ,  PRADEEPSUNDER GANESH ,  PARTHASARATHY SANGAM ,  JESSE C. BRANDEBURG

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/5011 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a “super” virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.

公开(公告)号：US20170118143A1

公开(公告)日：2017-04-27

申请号：US15400629

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： ELIEZER TAMIR ,  JESSE C. BRANDEBURG ,  ANIL VASUDEVAN

IPC: H04L12/879 ,  G06F9/48 ,  G06F9/52

CPC classification number: H04L49/90 ,  G06F9/327 ,  G06F9/4498 ,  G06F9/4812 ,  G06F9/526 ,  H04L49/901

Abstract: Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.