公开(公告)号：US20170288885A1

公开(公告)日：2017-10-05

申请号：US15086207

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Amirali Khatib Zadeh ,  Shekoufeh Qawami ,  Abhranil Maiti

IPC: H04L9/32 ,  G06F12/02 ,  G06F12/14

CPC classification number: H04L9/3278 ,  G06F12/0246 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/7201 ,  G09C1/00

Abstract: In one embodiment, an apparatus comprises: a challenger logic to issue a challenge to a responder logic, the challenge including an address of a portion of an array of a non-volatile memory; and the responder logic to receive the challenge and read data from the portion of the array at a read time less than a lockout period and at a demarcation voltage. The challenger logic may be configured to verify the challenge if the read data matches an expected read value, where the expected read value is determined based on configuration parameter information including compensation data associated with the portion of the array. Other embodiments are described and claimed.