公开(公告)号：US20240345966A1

公开(公告)日：2024-10-17

申请号：US18293858

申请日：2022-03-04

Applicant: Sony Group Corporation

Inventor： Yuuichi Nakamura

IPC: G06F12/14 ,  G06F12/0871

CPC classification number: G06F12/1466 ,  G06F12/0871 ,  G06F2212/1052

Abstract: An information processing device (100) includes a plurality of CPUs (1), a plurality of cache memories (2) associated with the plurality of CPUs (1), and a main memory (3), each of the plurality of CPUs (1) acquires a lock for exclusively accessing data in the main memory (3), and then accesses the data, data related to access of a corresponding CPU (1) and a lock ID for specifying the lock related to the access are associated and written in a cache 10 line of each of the plurality of cache memories (2), and a cache line of each of the plurality of cache memories (2) is flushed when a CPU (1) other than the corresponding CPU (1) acquires the lock specified based on the lock ID written in the cache line.

公开(公告)号：US12105644B2

公开(公告)日：2024-10-01

申请号：US18198782

申请日：2023-05-17

Applicant: Lodestar Licensing Group LLC

Inventor： Nathaniel J. Meier ,  Brenton P. Van Leeuwen

IPC: G06F12/14 ,  G06F3/06 ,  G06F21/62 ,  G06F21/79 ,  G11C11/4074 ,  G11C17/16 ,  H04L9/32

CPC classification number: G06F12/1433 ,  G06F12/1466 ,  G06F21/79 ,  G11C11/4074 ,  G11C17/16 ,  G06F3/0622 ,  G06F3/0637 ,  G06F12/14 ,  G06F12/1458 ,  G06F2212/1052

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

公开(公告)号：US12050701B2

公开(公告)日：2024-07-30

申请号：US17833515

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael LeMay ,  David M. Durham

IPC: G06F21/60 ,  G06F9/30 ,  G06F9/32 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/14 ,  G06F21/12 ,  G06F21/62 ,  G06F21/72 ,  G06F21/79 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14

CPC classification number: G06F21/602 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0646 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1408 ,  G06F12/1458 ,  G06F12/1466 ,  G06F21/12 ,  G06F21/6227 ,  G06F21/72 ,  G06F21/79 ,  H04L9/0637 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/0869 ,  H04L9/0894 ,  H04L9/14 ,  G06F2009/45587 ,  G06F2212/1052 ,  H04L2209/125

Abstract: Technologies disclosed herein provide cryptographic computing. An example method comprises executing a first instruction of a first software entity to receive a first input operand indicating a first key associated with a first memory compartment of a plurality of memory compartments stored in a first memory unit, and execute a cryptographic algorithm in a core of a processor to compute first encrypted contents based at least in part on the first key. Subsequent to computing the first encrypted contents in the core, the first encrypted contents are stored at a memory location in the first memory compartment of the first memory unit. More specific embodiments include, prior to storing the first encrypted contents at the memory location in the first memory compartment and subsequent to computing the first encrypted contents in the core, moving the first encrypted contents into a level one (L1) cache outside a boundary of the core.

公开(公告)号：US20240220427A1

公开(公告)日：2024-07-04

申请号：US18605301

申请日：2024-03-14

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： Shreyas Shah ,  George Apostol, JR. ,  Nagarajan Subramaniyan ,  Jack Regula ,  Jeffrey S. Earl

IPC: G06F13/16 ,  G06F12/06 ,  G06F12/0815 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/14 ,  G06F13/40 ,  G06F13/42 ,  G06N20/00

CPC classification number: G06F13/1668 ,  G06F12/0646 ,  G06F12/0815 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/1466 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026 ,  G06N20/00

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

公开(公告)号：US12007912B2

公开(公告)日：2024-06-11

申请号：US17814395

申请日：2022-07-22

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Lance Walker Dover ,  Tommaso Vali ,  Walter Di Francesco

IPC: G06F12/14 ,  G11C16/04 ,  G11C16/22

CPC classification number: G06F12/1466 ,  G11C16/22 ,  G06F2212/1052 ,  G11C16/0483

Abstract: In some implementations, a memory device may resolve a set of latches of a NAND page buffer to a set of initialized values. The memory device may obtain a NAND page buffer initialized data set from the set of initialized values of the set of latches. The memory device may generate a security key using the NAND page buffer initialized data set.

公开(公告)号：US11989438B2

公开(公告)日：2024-05-21

申请号：US17949981

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679 ,  G06F12/1466

Abstract: Methods, systems, and devices for secure self-purging memory partitions are described. Systems, techniques and devices are described herein in which data stored in a portion of a secure partition of memory may be removed from the secure partition. In some examples, a portion of secure partition may be allocated as self-purging memory such that data stored therein may be selectively removed in response to a logic address associated with the data being overwritten. In some cases, the data may be removed by programming the memory cells associated with the data to a specific voltage distribution. In some cases, the secure partition may include separate portions having different sets of operating parameters for access operations.

公开(公告)号：US11921645B2

公开(公告)日：2024-03-05

申请号：US17946762

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Prashant Dewan ,  Abhishek Basak ,  David M. Durham

IPC: G06F21/60 ,  G06F12/0831 ,  G06F12/14 ,  G06F13/28 ,  G06F21/78 ,  G06F21/85

CPC classification number: G06F12/1408 ,  G06F12/0835 ,  G06F12/1466 ,  G06F13/28 ,  G06F21/602 ,  G06F21/78 ,  G06F21/85 ,  G06F2212/1052 ,  G06F2212/402

Abstract: The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various embodiments. Historically, DDIO has enabled performance advantages that have outweighed its security risks. DDIO circuitry may be configured to secure DDIO data by using encryption circuitry that is manufactured for use in communications with main memory along the direct memory access (DMA) path. DDIO circuitry may be configured to secure DDIO data by using DDIO encryption circuitry manufactured for use by or manufactured within the DDIO circuitry. Enabling encryption and decryption in the DDIO path by the DDIO circuitry has the potential to close a security gap in modern data central processor units (CPUs).

公开(公告)号：US20240061943A1

公开(公告)日：2024-02-22

申请号：US18499133

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Ramya Jayaram Masti

IPC: G06F21/60 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/48 ,  G06F21/72 ,  H04L9/06 ,  G06F12/06 ,  G06F12/0875 ,  G06F21/79 ,  G06F9/455 ,  G06F12/0811 ,  G06F21/12 ,  H04L9/08 ,  G06F12/14 ,  G06F9/32 ,  G06F9/50 ,  G06F12/02 ,  H04L9/14 ,  G06F21/62

CPC classification number: G06F21/602 ,  G06F12/0897 ,  G06F9/30101 ,  G06F9/30178 ,  G06F9/48 ,  G06F21/72 ,  H04L9/0637 ,  G06F12/0646 ,  G06F12/0875 ,  G06F21/79 ,  G06F9/45558 ,  G06F12/0811 ,  G06F21/12 ,  H04L9/0861 ,  G06F12/1408 ,  G06F12/1466 ,  G06F9/321 ,  G06F9/5016 ,  G06F12/0207 ,  H04L9/0869 ,  H04L9/14 ,  G06F9/30043 ,  H04L9/0822 ,  H04L9/0894 ,  G06F12/1458 ,  G06F21/6227 ,  H04L2209/125 ,  G06F2212/1052 ,  G06F2009/45587

Abstract: Technologies disclosed herein provide cryptographic computing. An example method comprises storing, in a register, an encoded pointer to a memory location, where first context information is stored in first bits of the encoded pointer and a slice of a memory address of the memory location is encrypted and stored in second bits of the encoded pointer. The method further includes decoding the encoded pointer to obtain the memory address of the memory location, using the memory address obtained by decoding the encoded pointer to access encrypted data at the memory location, and decrypting the encrypted data based on a first key and a first tweak value. The first tweak value includes one or more bits derived, at least in part, from the encoded pointer.

公开(公告)号：US11899595B2

公开(公告)日：2024-02-13

申请号：US17929650

申请日：2022-09-02

Applicant: Amazon Technologies, Inc.

Inventor： Jason G. McHugh ,  Praveen Kumar Gattu ,  Michael A. Ten-Pow ,  Derek Ernest Denny-Brown, II

IPC: G06F12/14 ,  G06F16/16 ,  G06F16/18 ,  G06F16/23 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F12/1466 ,  G06F3/067 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0652 ,  G06F3/0671 ,  G06F3/0673 ,  G06F11/1435 ,  G06F11/1453 ,  G06F16/162 ,  G06F16/1873 ,  G06F16/2329 ,  G06F2201/80 ,  G06F2201/84 ,  G06F2212/1052

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

公开(公告)号：US11880313B2

公开(公告)日：2024-01-23

申请号：US18158519

申请日：2023-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegyu Lee ,  Jisoo Kim ,  Young-Jin Park ,  Bo-Ram Shin

IPC: G06F12/00 ,  G06F12/14 ,  G06F11/10 ,  G06F11/14 ,  G06F12/02

CPC classification number: G06F12/145 ,  G06F12/1441 ,  G06F12/1466 ,  G06F11/1072 ,  G06F11/1441 ,  G06F12/0246 ,  G06F2212/1052 ,  G06F2212/7206

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.