公开(公告)号：US10812075B2

公开(公告)日：2020-10-20

申请号：US16417511

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Linda K. Sun ,  Maria Jose Garcia Garcia de Leon ,  Raul Enriquez Shibayama ,  Abraham Isidoro Munoz ,  Carlos Eduardo Lozoya Lopez

IPC: H03K19/00 ,  H03K19/0175 ,  G06F13/40 ,  H04L25/02

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

公开(公告)号：US20190280691A1

公开(公告)日：2019-09-12

申请号：US16417511

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Linda K. Sun ,  Maria Jose Garcia Garcia de Leon ,  Raul Enriquez Shibayama ,  Abraham Isidoro Munoz ,  Carlos Eduardo Lozoya Lopez

IPC: H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  G06F13/40

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.