公开(公告)号：US20250124994A1

公开(公告)日：2025-04-17

申请号：US18986494

申请日：2024-12-18

Applicant: Intel Corporation

Inventor： Dat T. LE ,  George VERGIS ,  Alejandro LARIOS

IPC: G11C29/02 ,  G11C29/14 ,  G11C29/44

Abstract: Methods and apparatus for DDR5 DIMM power fail monitor to prevent I/O reverse-bias current. An apparatus is configured to be implemented in a host system including a processor having an integrated memory controller (iMC) coupled to one or more DIMMs having an onboard Power Management Integrated Circuit (PMIC). The apparatus includes circuitry to monitor an operating state for a host voltage regulator (VR) providing input power to the processor and monitor an operating state of the PMIC for each of the one or more DIMMs. In response to detecting a fault condition of the host VR or a PMIC for a DIMM, the apparatus prevents reverse bias voltage in circuitry in at least one of the iMC and the one or more DIMMs. The apparatus may implement a finite state machine (FSN) having a plurality of defined states including a fault state used to indicate detection of the fault condition.