公开(公告)号：US20240172131A1

公开(公告)日：2024-05-23

申请号：US18548914

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Wayne BALLANTYNE ,  Chuanzhao YU ,  Ali AZAM ,  Gregory CHANCE ,  Lichung Tony CHANG

IPC: H04W52/34 ,  H04L5/00 ,  H04W72/044 ,  H04W72/1273

CPC classification number: H04W52/34 ,  H04L5/0048 ,  H04W72/0473 ,  H04W72/1273

Abstract: Methods and devices configured to determine, for a slot including a plurality of symbols allocated for downlink data, a downlink data block allocation scheme with a number of blocks of downlink data that remain constant or monotonically decrease starting at a designated symbol of the plurality of symbols allocated for downlink data; generate a voltage profile corresponding to the downlink data block allocation scheme, where the voltage profile includes a plurality of bias voltages; and apply a bias voltage selected from the plurality of bias voltages to a power amplifier in a transmission chain of the base station.

公开(公告)号：US20220407474A1

公开(公告)日：2022-12-22

申请号：US17351283

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Jaeyoung CHOI ,  Ali AZAM

IPC: H03F1/52 ,  H03F3/24 ,  H04B1/38

Abstract: A power amplifier may be configured to operate in an on state and an off state. The power amplifier may include a plurality of transistors and an impedance controller circuit. The plurality of transistors may be electrically coupled to an electrical ground and an output of the power amplifier. The impedance controller circuit may be electrically coupled to the plurality of transistors and a reference voltage. The impedance controller circuit may be configured to provide the reference voltage to the plurality of transistors when the power amplifier is in the off state to cause a leakage current to flow between the reference voltage and the electrical ground.

公开(公告)号：US20220416770A1

公开(公告)日：2022-12-29

申请号：US17356564

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ali AZAM ,  Ashoke RAVI ,  Benjamin JANN

IPC: H03K5/00 ,  G06F7/68 ,  H03K5/02

Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

公开(公告)号：US20220416735A1

公开(公告)日：2022-12-29

申请号：US17358019

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Ali AZAM ,  Wayne BALLANTYNE ,  LiChung CHANG

IPC: H03F3/24 ,  H03F1/32

Abstract: A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.