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公开(公告)号：US20220407226A1
公开(公告)日：2022-12-22
申请号：US17352394
申请日：2021-06-21
Applicant: Intel Corporation
Inventor： Benjamin JANN , Ashoke RAVI
Abstract: A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.
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公开(公告)号：US20220201600A1
公开(公告)日：2022-06-23
申请号：US17126124
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Ehud RESHEF , Ofir DEGANI , Roya DOOSTNEJAD , Avishay FRIEDMAN , Nevo IDAN , Eytan MANN , Ashoke RAVI , Gadi SHOR , Shahar GROSS , Ofir KLEIN , Chen KOJOKARO
Abstract: In various aspects, a radio communication device is described including a housing, a plurality of radiohead circuits attached to the housing, baseband circuitry connected to the plurality of radiohead circuits via a digital interface; and one or more processors configured to select one or more radiohead circuits of the plurality of radiohead circuits for communication with another radio communication device to fulfill one or more predefined selection criteria with respect to a quality of a communication with the other radio communication device using the one or more selected radiohead circuits and to control the baseband circuitry to perform communication with the other radio communication device using the one or more selected radiohead circuits.
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3.发明公开公开(公告)号：US20230308193A1
公开(公告)日：2023-09-28
申请号：US18041804
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Rotem BANIN , Ofir DEGANI , Shahar GROSS , Run LEVINGER , Eytan MANN , Ashoke RAVI , Ehud RESHEF , Amir RUBIN , Eran SEGEV , Evgeny SHUMAKER
CPC classification number: H04B17/14 , H04W56/0015
Abstract: In various aspects of this disclosure, a communication device is provided. The communication device may include a first radiohead circuit including a first transceiver chain configured to transmit a first radio frequency signal associated with a first transmission configuration and to transmit a second radio frequency signal associated with a second transmission configuration a second radiohead circuit comprising a second transceiver chain configured to receive the first radio frequency signal and the second radio frequency signal, and one or more processors configured to determine a first signal parameter associated with the first radio frequency signal received at the second transceiver chain and a second signal parameter associated with the second radio frequency signal received at the second transceiver chain, and to determine a preferred transmission configuration for the first transceiver chain by using the first signal parameter and the second signal parameter.
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公开(公告)号：US20230216409A1
公开(公告)日：2023-07-06
申请号：US17999856
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Ashoke RAVI , Ofir DEGANI , Harish KRISHNAMURTHY , Shahar WOLF , Sally AMIN , Suhwan KIM
CPC classification number: H02M3/1582 , H02M1/007 , H02M1/0025 , H02M1/0045
Abstract: A single inductor multiple output DC-to-DC converter may be configured as a buck-boost converter. The converter may include an inductor, a plurality of switches coupled to the inductor to control energizing and deenergizing phases of the inductor, and a plurality of output rails. Each of the plurality of output rails may include at least one switch, which is configured to connect the output rail to the inductor of the buck-boost converter. Depending on the energizing and deenergizing patterns of the inductor, and the state of the one or more switches, the various output rails may be supplied with a plurality of different output voltages and / or output currents. Any of a plurality of regulating strategies may be utilized to further control the output voltages and / or the output currents.
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公开(公告)号：US20250112603A1
公开(公告)日：2025-04-03
申请号：US18374696
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Ashoke RAVI , Ofir DEGANI , Sashank KRISHNAMURTHY , Soumya GUPTA
Abstract: An amplifier structure may include a first amplifier substructure having a first amplifier and a first filter structure and provide a first high frequency output signal and a first low frequency output signal having a frequency lower than a frequency of the first high frequency output signal. It may include a second amplifier substructure having a second amplifier and a second filter structure and provide a second high frequency output signal and a second low frequency output signal having a frequency lower than the frequency of the second high frequency output signal. It may include a first combination node configured to receive the first high frequency output signal and the second low frequency output signal and to provide a first amplified signal, and a second combination node configured to receive the first low frequency output signal and the second high frequency output signal and to provide a second amplified signal.
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Patent Agency Ranking
公开(公告)号：US20240223416A1
公开(公告)日：2024-07-04
申请号：US18147736
申请日：2022-12-29
Applicant: Intel Corporation
Inventor： Hossein ALAVI , Elan BANIN , Ofir DEGANI , Ashoke RAVI
CPC classification number: H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0026
Abstract: A system includes a processor configured to determine a frequency offset between a first local oscillator and a second local oscillator using a combined radio signal received at a first transceiver circuit; wherein the combined radio signal comprises a first signal transmitted by the first transceiver circuit and a second signal transmitted by a second transceiver circuit.
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公开(公告)号：US20230093115A1
公开(公告)日：2023-03-23
申请号：US17482480
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： Assaf BEN-BASSAT , Elan BANIN , Alaa BEIDAS , Ofir DEGANI , Ashoke RAVI
Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable and frequency-controllable oscillator that is configured to generate an oscillator signal. The spiking neuron may further include a spike signal detector that is configured to generate spike detection signals in response to detection of input spike signals. The spike signal detector may generate the spike detection signals based on the oscillator signal. The spiking neuron may further include a neuron structure that is configured to provide an output spike signal based on the spike detection signals and the oscillator signal.
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公开(公告)号：US20240120929A1
公开(公告)日：2024-04-11
申请号：US17956835
申请日：2022-09-30
Applicant: Intel Corporation
Inventor： Ofir DEGANI , Run LEVINGER , Ashoke RAVI
IPC: H03L7/099
CPC classification number: H03L7/0998
Abstract: The present disclosure relates to a signal generator including: a plurality of interpolators, each interpolator being configured to: receive a first input signal having a first phase, and a second input signal having a second phase; generate a plurality of interpolated signals based on a plurality of interpolations of the input signals, each interpolated signal having a respective phase based on the respective interpolation, and combine the interpolated signals to provide an output signal; the plurality of interpolators including: a first plurality of interpolators, each interpolator being configured to receive as input signals a first reference signal and a second reference signal; and a second plurality of interpolators, each interpolator being configured to receive as first input signal an output signal from an interpolator of the first plurality of interpolators and as second input signal another output signal from another interpolator of the first plurality of interpolators.
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公开(公告)号：US20230361802A1
公开(公告)日：2023-11-09
申请号：US18029932
申请日：2020-11-03
Applicant: Intel Corporation
Inventor： Jayprakash THAKUR , Ofir DEGANI , Ronen KRONFELD , Ehud RESHEF , Seong-Youp J. SUH , Tal SHOSHANA , Eytan MANN , Maruti TAMRAKAR , Ashoke RAVI , Jose Rodrigo CAMACHO PEREZ , Timo Sakari HUUSARI , Eli BOROKHOVICH , Amir RUBIN , Ofer BENJAMIN , Tae Young YANG , Harry SKINNER , Kwan ho LEE , Jaejin LEE , Dong-Ho Han , Shahar GROSS , Eran SEGEV , Telesphor KAMGAING
IPC: H04B1/40
CPC classification number: H04B1/40
Abstract: In various aspects, a radio frequency circuit is provided. The radio frequency circuit may include a substrate that may include a radio frequency front-end to antenna (RF FE-to-Ant) connector. The RF FE-to-Ant connector may include a conductor track structure and a substrate connection structure coupled to the conductor track structure. The substrate may include radio frequency front-end circuitry monolithically integrated in the substrate. The substrate connection structure may include at least one of a solderable structure, a weldable structure, or an adherable structure. The substrate connection structure may be configured to form at least one radio frequency signal interface with an antenna circuit connection structure of a substrate-external antenna circuit. The substrate may include an edge region. The substrate connection structure may be disposed in the edge region.
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10.发明申请公开(公告)号：US20220416770A1
公开(公告)日：2022-12-29
申请号：US17356564
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Ali AZAM , Ashoke RAVI , Benjamin JANN
Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.
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