公开(公告)号：US20180285732A1

公开(公告)日：2018-10-04

申请号：US15475029

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Dileep J. KURIAN ,  Ambili V ,  Dilin DIVAKAR

IPC: G06N3/08 ,  G11C7/22 ,  G06N3/04 ,  G06F1/32 ,  G11C5/14

Abstract: In one embodiment, a system employing selective noise tolerance modes of memory operation in accordance with one aspect of the present description can reduce levels of memory operation power consumption as compared to those achieved by many prior devices. In one embodiment, each noise tolerance mode has an associated level of input power to a memory. For example, in one embodiment, the greater the degree of tolerance for noise in the data of a workload being processed, the greater the reduction in memory input power and the greater the resultant reduction in power consumption. Other aspects and advantages are described.

公开(公告)号：US20170123979A1

公开(公告)日：2017-05-04

申请号：US14925959

申请日：2015-10-28

Applicant: Intel Corporation

Inventor： Ambili V ,  Dileep Kurian

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F2212/1016 ,  Y02D10/13

Abstract: Devices and systems for managing partial cache misses in multiple cache lines of a memory cache are disclosed and described, including associated methods.