公开(公告)号：US20220360359A1

公开(公告)日：2022-11-10

申请号：US17869370

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Alon MEISLER ,  Ehud SHOOR ,  Amir MEZER ,  Tsion VIDAL

IPC: H04K1/04

Abstract: Examples described herein relate to a network interface device that includes first circuitry to perform a first scrambling operation on input data; second circuitry to perform a second scrambling operation on the input data; and third circuitry to select the second scrambled input data based on the first scrambled input data including a data sequence that is associated with receiver malfunction and the second scrambled input data including the data sequence that is associated with receiver malfunction.

公开(公告)号：US20190044627A1

公开(公告)日：2019-02-07

申请号：US15985136

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Mor COHEN ,  Amir MEZER ,  Golan PERRY ,  Adee Ofir RAN

IPC: H04B17/29 ,  H04B1/16 ,  H04L12/26

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.