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公开(公告)号：US20240428851A1
公开(公告)日：2024-12-26
申请号：US18212922
申请日：2023-06-22
Applicant: Intel Corporation
Inventor： Amlan GHOSH , Saroj SATAPATHY , Anandraj DEVARAJAN , Jaydeep KULKARNI , Feroze MERCHANT
IPC: G11C11/419 , G06F12/084 , G11C11/412
Abstract: Some embodiments relate generally to memory arrays having complementary bitlines. With some implementations, charge sharing to facilitate midrail read operations may be incorporated therein.
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