公开(公告)号：US20240428851A1

公开(公告)日：2024-12-26

申请号：US18212922

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Amlan GHOSH ,  Saroj SATAPATHY ,  Anandraj DEVARAJAN ,  Jaydeep KULKARNI ,  Feroze MERCHANT

IPC: G11C11/419 ,  G06F12/084 ,  G11C11/412

Abstract: Some embodiments relate generally to memory arrays having complementary bitlines. With some implementations, charge sharing to facilitate midrail read operations may be incorporated therein.

公开(公告)号：US20180166145A1

公开(公告)日：2018-06-14

申请号：US15373048

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Minki CHO ,  Jaydeep KULKARNI ,  Carlos TOKUNAGA ,  Muhammad KHELLAH ,  James TSCHANZ

IPC: G11C29/12 ,  G11C5/14 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C11/4125 ,  G11C11/413 ,  G11C29/12005 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/1206 ,  G11C2029/5004

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

公开(公告)号：US20180336161A1

公开(公告)日：2018-11-22

申请号：US15777249

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Farhana SHEIKH ,  Ankit SHARMA ,  Jaydeep KULKARNI

IPC: G06F17/14

Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.