公开(公告)号：US11721554B2

公开(公告)日：2023-08-08

申请号：US16356402

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Anant Jahagirdar ,  Chytra Pawashe ,  Aaron Lilak ,  Myra McDonnell ,  Brennen Mueller ,  Mauro Kobrinsky

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L21/20 ,  H01L21/56 ,  H01L21/02 ,  H01L21/603

CPC classification number: H01L21/2007 ,  H01L21/0226 ,  H01L21/56 ,  H01L21/603

Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.