公开(公告)号：US12047090B2

公开(公告)日：2024-07-23

申请号：US17635001

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Filipe De Andrade Tabarani Santos ,  Andreas Roithmeier ,  Timo Gossmann ,  Syed Ahmed Aamir ,  Rinaldo Zinke

IPC: H03M1/00 ,  H03F3/20 ,  H03M1/66

CPC classification number: H03M1/662 ,  H03F3/20 ,  H03F2200/451

Abstract: A RFDAC comprising an array of unit-cell power amplifiers, wherein the array comprises a first plurality of unit-cell power amplifiers, a second plurality of unit-cell power amplifiers, and a third plurality of unit-cell power amplifiers; wherein the first plurality of unit-cell power amplifiers are configured to operate in accordance with a first clock; wherein the second plurality of unit-cell power amplifiers are configured to operate in accordance with a second clock; wherein the third plurality of unit-cell power amplifiers are configured to operate in accordance with the first clock or the second clock. The RFDAC also comprising a decoder configured to output the first clock and an enablement signal of the first clock for the first plurality; output the second clock and an enablement signal of the second clock for the second plurality; distinguish between the first clock and the second clock for the third plurality.

公开(公告)号：US10483911B2

公开(公告)日：2019-11-19

申请号：US15392527

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Svetozar Broussev ,  Andreas Jörn Leistner ,  Andreas Roithmeier ,  Thomas Gustedt

IPC: H03B5/12

Abstract: Various designs for MOS transistor-based RF switch topologies for high speed capacitive tuning of oscillators switch circuits include a main switch device comprising a gate connected to a control terminal, a drain connected to a first terminal that is connected to the first capacitor, and a source connected to a second terminal that is connected to the second capacitor. The switch further comprises a first NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the first terminal. The switch further comprises a second NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the second terminal. The switch further comprises a pair of PMOS devices each having drains connected respectively to the first and second terminals.