公开(公告)号：US20250112037A1

公开(公告)日：2025-04-03

申请号：US18374603

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Mark KOEPER ,  Andrew MOORE ,  Sreenivas KOSARAJU ,  Nicholas J. KYBERT ,  Mengcheng LU ,  Atul MADHAVAN ,  Sudipto NASKAR ,  Wei Z. QIU ,  Tiffany R. ZINK

IPC: H01L21/02 ,  H01L23/48 ,  H01L29/10 ,  H01L29/423

Abstract: Selective dielectric growth directing contact to gate or contact to trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric-on-metal (DOM) layer is on and is confined to the uppermost surface of the conductive trench contact structures. A gate contact via is on a gate electrode of one of the plurality of gate structures.