公开(公告)号：US20250022939A1

公开(公告)日：2025-01-16

申请号：US18900094

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Tahir GHANI ,  Atul MADHAVAN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

公开(公告)号：US20250112037A1

公开(公告)日：2025-04-03

申请号：US18374603

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Mark KOEPER ,  Andrew MOORE ,  Sreenivas KOSARAJU ,  Nicholas J. KYBERT ,  Mengcheng LU ,  Atul MADHAVAN ,  Sudipto NASKAR ,  Wei Z. QIU ,  Tiffany R. ZINK

IPC: H01L21/02 ,  H01L23/48 ,  H01L29/10 ,  H01L29/423

Abstract: Selective dielectric growth directing contact to gate or contact to trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric-on-metal (DOM) layer is on and is confined to the uppermost surface of the conductive trench contact structures. A gate contact via is on a gate electrode of one of the plurality of gate structures.

公开(公告)号：US20240006322A1

公开(公告)日：2024-01-04

申请号：US18370198

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

CPC classification number: H01L23/535 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/518 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0276

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20220310516A1

公开(公告)日：2022-09-29

申请号：US17841479

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20200043850A1

公开(公告)日：2020-02-06

申请号：US16542960

申请日：2019-08-16

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Atul MADHAVAN ,  Christopher P. AUTH

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L21/308 ,  H01L29/66 ,  H01L27/11 ,  H01L29/08 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/762 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.

公开(公告)号：US20220102279A1

公开(公告)日：2022-03-31

申请号：US17131701

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Abhishek JAIN ,  Jinhong SHIN ,  Anant H. JAHAGIRDAR

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a single dielectric layer above a substrate. A plurality of conductive lines is in an upper portion of the single dielectric layer above a lower portion of the single dielectric layer. A carbon dopant region is in the upper portion of the single dielectric layer, the carbon dopant region between adjacent ones of the plurality of conductive lines.

公开(公告)号：US20220068802A1

公开(公告)日：2022-03-03

申请号：US17133080

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Gokul MALYAVANATHAM ,  Philip YASHAR ,  Mark KOEPER ,  Bharath BANGALORE RAJEEVA ,  Krishna T. MARLA ,  Umang DESAI ,  Harry B. RUSSELL

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, a second conductive interconnect line in a second ILD layer above the first ILD layer, and a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer. In another example, a method of fabricating an integrated circuit structure includes forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer, etching a hanging via that lands on the etch stop layer, and performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.

公开(公告)号：US20190164890A1

公开(公告)日：2019-05-30

申请号：US15859415

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Atul MADHAVAN ,  Christopher P. AUTH

IPC: H01L23/528 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.

公开(公告)号：US20240347465A1

公开(公告)日：2024-10-17

申请号：US18753766

申请日：2024-06-25

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L23/535 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/518 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/31144 ,  H01L29/45

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20230144607A1

公开(公告)日：2023-05-11

申请号：US18093776

申请日：2023-01-05

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Tahir GHANI ,  Atul MADHAVAN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H10B10/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

CPC classification number: H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7843 ,  H01L27/0886 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/0653 ,  H01L21/823431 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/76816 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/165 ,  H01L21/76846 ,  H01L21/76849 ,  H01L29/7845 ,  H01L21/76834 ,  H01L29/41791 ,  H01L21/76801 ,  H10B10/12 ,  H01L29/0649 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7854 ,  H01L21/28518 ,  H01L23/5329 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/41783 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/76883 ,  H01L21/76885 ,  H01L29/665 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.