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1.发明申请公开(公告)号：US20220321321A1
公开(公告)日：2022-10-06
申请号：US17833498
申请日：2022-06-06
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew Reinders , Rafael Misoczki , Rosario Cammarota , Manoj Sastry
Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.
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公开(公告)号：US20220094518A1
公开(公告)日：2022-03-24
申请号：US17025344
申请日：2020-09-18
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew Reinders , Rafael Misoczki , Rosario Cammarota , Manoj Sastry
Abstract: Embodiments are directed to low circuit depth homomorphic encryption evaluations. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, determine two coefficients of the ciphertext for HE evaluation, input the two coefficients as a first operand and a second operand to a pipeline multiplier for low circuit depth HE evaluation, perform combinatorial multiplication between the first operand and portions of the second operand, accumulate results of the combinatorial multiplication at each stage of the pipeline multiplier, and perform reduction with Mersenne prime modulus on a resulting accumulated output of the combinatorial multipliers of the pipeline multiplier.
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公开(公告)号：US11569994B2
公开(公告)日：2023-01-31
申请号：US17356972
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew Reinders , Manoj Sastry
Abstract: An accelerator includes polynomial multiplier circuitry including at least one modulus multiplier operating according to a mode. The at least one modulus multiplier include a multiplier to multiply two polynomial coefficients to generate a multiplication result, a power of two reducer to reduce the multiplication result to a reduced multiplication result when the mode is a power of two mode, and a prime modulus reducer to reduce the multiplication result to the reduced multiplication result when the mode is a prime modulus mode.
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Patent Agency Ranking
4.发明申请公开(公告)号：US20220094517A1
公开(公告)日：2022-03-24
申请号：US17025337
申请日：2020-09-18
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew Reinders , Rafael Misoczki , Rosario Cammarota , Manoj Sastry
Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus.
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公开(公告)号：US20190044732A1
公开(公告)日：2019-02-07
申请号：US15856179
申请日：2017-12-28
Applicant: Intel Corporation
Inventor： Andrew Reinders , Manoj Sastry , Santosh Ghosh , Rafael Misoczki
Abstract: A technique includes generating a direct anonymous attestation (DAA)-based signature to prove an electronic device is a member of a group. Generating the signature includes determining a reciprocal of a prime modulus, and determining the reciprocal of the prime modulus comprises left bit shifting a Barrett multiplier by a predetermined number of bits and multiplying a result of the left bit shifting of the Barrett multiplier with the prime modulus.
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6.发明授权公开(公告)号：US11777707B2
公开(公告)日：2023-10-03
申请号：US17833498
申请日：2022-06-06
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew Reinders , Rafael Misoczki , Rosario Cammarota , Manoj Sastry
IPC: H04L9/00 , H04L9/06 , G06F7/72 , G09C1/00 , G06F21/72 , G06F7/487 , G06F21/60 , G06N3/063 , G06N20/00 , G06N3/08
CPC classification number: H04L9/008 , G06F7/722 , G06N3/08 , H04L9/0618
Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.
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公开(公告)号：US20220417019A1
公开(公告)日：2022-12-29
申请号：US17356972
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew Reinders , Manoj Sastry
Abstract: An accelerator includes polynomial multiplier circuitry including at least one modulus multiplier operating according to a mode. The at least one modulus multiplier include a multiplier to multiply two polynomial coefficients to generate a multiplication result, a power of two reducer to reduce the multiplication result to a reduced multiplication result when the mode is a power of two mode, and a prime modulus reducer to reduce the multiplication result to the reduced multiplication result when the mode is a prime modulus mode.
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公开(公告)号：US10833868B2
公开(公告)日：2020-11-10
申请号：US15856179
申请日：2017-12-28
Applicant: Intel Corporation
Inventor： Andrew Reinders , Manoj Sastry , Santosh Ghosh , Rafael Misoczki
Abstract: A technique includes generating a direct anonymous attestation (DAA)-based signature to prove an electronic device is a member of a group. Generating the signature includes determining a reciprocal of a prime modulus, and determining the reciprocal of the prime modulus comprises left bit shifting a Barrett multiplier by a predetermined number of bits and multiplying a result of the left bit shifting of the Barrett multiplier with the prime modulus.
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