公开(公告)号：US20240256350A1

公开(公告)日：2024-08-01

申请号：US18103087

申请日：2023-01-30

Applicant: INGONYAMA LTD.

Inventor： Michael ASA ,  Omer SHLOMOVITS ,  Daniel SHTERMAN ,  Yuval DOMB

IPC: G06F9/50 ,  G06F7/72 ,  G06F9/48

CPC classification number: G06F9/5044 ,  G06F7/722 ,  G06F9/4881 ,  G06F9/5016

Abstract: A multi-thread processor computes a function requiring only modular additions and multiplications. Memories store constants, multi-bit elements, and multiple instruction sets. A multiplier receives first and second multiplier operands, generates their product, which is fed to an adder as a first operand and added to a second adder operand, the sum being stored in an accumulator memory. Each instruction set is executed on a successive clock, and includes instructions for defining respective addresses in the memories from which constants, elements and sums are to be accessed. A scheduler maintains a schedule of threads executable by the processor in parallel, and is configured on each successive clock to cycle through the threads and initiate a first available thread. Selectors responsive to instructions received from the program memory select the required multiplier and adder operands. A multi-core system executes multiple parallel threads on multiple processors allowing complex functions to be computed efficiently.

公开(公告)号：US20240028299A1

公开(公告)日：2024-01-25

申请号：US18188382

申请日：2023-03-22

Applicant: SK hynix Inc.

Inventor： Seong Ju LEE

IPC: G06F7/544 ,  G06F7/72 ,  G06F7/49

CPC classification number: G06F7/5443 ,  G06F7/722 ,  G06F7/49

Abstract: A multiplication and accumulation (MAC) operator includes a residue number generating circuit configured to generate a plurality of weight residue number data for weight data and a plurality of vector residue number data for the vector data by using a plurality of divisors, a multiplication circuit configured to generate a plurality of residue number multiplication data by performing a multiplication operation on the weight residue number data and the vector residue number data, an addition circuit configured to generate residue number multiplication addition data by performing an addition operation on the multiplication data, an accumulating circuit configured to generate residue number accumulation data by performing an accumulation operation on the residue number multiplication addition data and latch data, and a mixed radix conversion circuit configured to generate the MAC result data by using the divisors and the residue number accumulation data that is transmitted by the accumulating circuit.

公开(公告)号：US20230401037A1

公开(公告)日：2023-12-14

申请号：US18237859

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Erdinc OZTURK ,  Kirk S. YAP ,  Tomasz KANTECKI

IPC: G06F7/72

CPC classification number: G06F7/722 ,  G06F7/728

Abstract: Methods and apparatus for optimization techniques for modular multiplication algorithms. The optimization techniques may be applied to variants of modular multiplication algorithms, including variants of Montgomery multiplication algorithms and Barrett multiplication algorithms. The optimization techniques reduce the number of serial steps in Montgomery reduction and Barrett reduction. Modular multiplication operations involving products of integer inputs A and B may be performed in parallel to obtain a value C that is reduced to a residual RES. Modular multiplication and modular reduction operations may be performed in parallel. The number of serial steps in the modular reductions are reduced to L, where L serial steps, where w is a digit size in bits, and L is a number of digits of operands=[k/w].

公开(公告)号：US11777707B2

公开(公告)日：2023-10-03

申请号：US17833498

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  H04L9/06 ,  G06F7/72 ,  G09C1/00 ,  G06F21/72 ,  G06F7/487 ,  G06F21/60 ,  G06N3/063 ,  G06N20/00 ,  G06N3/08

CPC classification number: H04L9/008 ,  G06F7/722 ,  G06N3/08 ,  H04L9/0618

Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.

公开(公告)号：US20180181374A1

公开(公告)日：2018-06-28

申请号：US15807888

申请日：2017-11-09

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yun-Koo LEE ,  Dong-Geon LEE ,  Min-Kyu JOO ,  Yoen-Cheol LEE ,  Sang-Woon YANG

IPC: G06F7/523 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50 ,  G06F7/722 ,  G06F7/728

Abstract: An apparatus and method for modular multiplication. The modular multiplication apparatus includes a first operation unit for performing a first operation based on a structure of at least one of a serial multiplier and a serial squarer-based multiplier; a second operation unit for performing a second operation based on a structure of at least one of the serial multiplier and the serial squarer-based multiplier; an adder unit for outputting the sum of results of the first operation and the second operation, inputting an intermediate value stream to the first input unit, which calculates the product of the intermediate value stream and a zeta parameter, and outputting a High-Order Term as a result of Montgomery Modular Multiplication, wherein the first and second operation units output a result in digit-serial format in order from the least significant digit to the most significant digit.

公开(公告)号：US09753693B2

公开(公告)日：2017-09-05

申请号：US14208591

申请日：2014-03-13

Applicant: Imagination Technologies Limited

Inventor： Thomas Rose

IPC: G06F7/52 ,  G06F7/523 ,  G06F7/535 ,  G06F7/499 ,  G06F17/50

CPC classification number: G06F7/49947 ,  G06F7/4824 ,  G06F7/52 ,  G06F7/523 ,  G06F7/535 ,  G06F7/722 ,  G06F7/727 ,  G06F17/505 ,  G06F2207/5356

Abstract: A binary logic circuit is provided for determining a rounded value of px q , where p and q are coprime constant integers with p

公开(公告)号：US20160308676A1

公开(公告)日：2016-10-20

申请号：US15102637

申请日：2013-12-28

Applicant: Yang LU ,  Xiangzheng SUN ,  Nan Stan QIAO ,  INTEL CORPORATION

Inventor： Yang Lu ,  Xiangzheng Sun ,  Nan Qiao

IPC: H04L9/30 ,  G06F9/30 ,  G06F7/72

CPC classification number: H04L9/302 ,  G06F7/722 ,  G06F7/723 ,  G06F9/30007 ,  G06F9/3017 ,  G09C1/00

Abstract: A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a second 64-bit source operand having a second 64-bit value, indicates a third 64-bit source operand having a third 64-bit value, and indicates a fourth 64-bit source operand having a fourth 64-bit value. An execution unit is coupled with the decode unit. The execution unit is operable, in response to the instruction, to store a result. The result includes the first 64-bit value multiplied by the second 64-bit value added to the third 64-bit value added to the fourth 64-bit value. The execution unit may store a 64-bit least significant half of the result in a first 64-bit destination operand indicated by the instruction, and store a 64-bit most significant half of the result in a second 64-bit destination operand indicated by the instruction.

Abstract translation: 处理器包括解码指令译码单元。 该指令指示具有第一64位值的第一64位源操作数，指示具有第二64位值的第二64位源操作数，指示具有第三64位值的第三64位源操作数， 并且指示具有第四个64位值的第四个64位源操作数。 执行单元与解码单元耦合。 执行单元响应于该指令可操作以存储结果。 结果包括第一个64位值乘以加到第四个64位值的第三个64位值的第二个64位值。 执行单元可以将结果的64位最不重要的一半存储在由指令指示的第一个64位目标操作数中，并将结果的64位最高有效的一半存储在第二个64位目标操作数中， 指示。

公开(公告)号：US20120197956A1

公开(公告)日：2012-08-02

申请号：US13443049

申请日：2012-04-10

Applicant: Wieland FISCHER

Inventor： Wieland FISCHER

IPC: G06F7/52 ,  G06F11/00 ,  G06F7/50

CPC classification number: G06F7/722

Abstract: A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number.

Abstract translation: 一种用于减少相对于模数的输入数的计算单元，其中所述输入数具有不同意义的输入数部分，其中所述输入数部分表示相对于分割数的输入数，其中所述模量具有不同的模数部分 意义，并且其中模数部分表示相对于分割数的模数，包括用于使用所存储的最高有效部分的数量来估计输入数的整数除以模数的结果的单元，存储的最高有效部分 以及用于将估计结果存储在计算单元的存储器中的单元，以及用于基于从该数字的估计结果导出的模数乘积的乘积的乘积来计算减少结果的单元 。

公开(公告)号：US20110213819A1

公开(公告)日：2011-09-01

申请号：US13042284

申请日：2011-03-07

Applicant: Michel Douguet ,  Vincent Dupaquis

Inventor： Michel Douguet ,  Vincent Dupaquis

IPC: G06F7/487 ,  G06F7/58

CPC classification number: G06F7/722

Abstract: A modular multiplication method implemented in an electronic digital processing system takes advantage of the case where one of the operands W is known in advance or used multiple times with different second operands V to speed calculation. The operands V and W and the modulus M may be integers or polynomials over a variable X. A possible choice for the type of polynomials can be polynomials of the binary finite field GF(2N). Once operand W is loaded into a data storage location, a value P=└W·Xn+δ/M┘ is pre-computed by the processing system. Then when a second operand V is loaded, the quotient q{circle around ( )} for the product V·W being reduced modulo M is quickly estimated, q{circle around ( )}=└V·P/Xn+δ┘, optionally randomized, q′=q{circle around ( )}−E, and can be used to obtain the remainder r′=V·W−q′·M, which is congruent to (V·W) mod M. A final reduction can be carried out, and the later steps repeated with other second operands V.

Abstract translation: 在电子数字处理系统中实现的模乘法利用了预先知道操作数W之一或者用不同的第二操作数V多次使用以加速计算的情况。 操作数V和W以及模数M可以是变量X上的整数或多项式。多项式类型的可能选择可以是二进制有限域GF（2N）的多项式。 一旦操作数W被加载到数据存储位置，则处理系统预先计算值P =└W·Xn +δ/M。 然后当加载第二个操作数V时，对于产品V·W减M的商q {circle around（）}被快速估计，q {circle around（）} =└V·P / Xn +δ' 可选地随机化，q'= q {circle around（）} -E，并且可以用于获得与（V·W）mod M一致的余数r'= V·W-q'·M。最终 可以执行减少，并且随后的步骤与其他第二操作数V重复。

公开(公告)号：US07607165B2

公开(公告)日：2009-10-20

申请号：US10096038

申请日：2002-03-11

Applicant: Jonathon D. Mellott ,  Patrick Dennis Rugg

Inventor： Jonathon D. Mellott ,  Patrick Dennis Rugg

IPC: H04L9/00

CPC classification number: G06F7/722 ,  G06F7/72

Abstract: The subject invention relates to a method and apparatus for multiplication of numbers. In a specific embodiment, the subject invention can be used to perform sequential multiplication. The subject invention also pertains to a method and apparatus for modular reduction processing of a number or product of two numbers. In a specific embodiment, sequential multiplication can be incorporated to perform modular reduction processing. The subject method and apparatus can also be utilized for modular exponentiation of large numbers. In a specific embodiment, numbers larger than or equal to 2128 or even higher can be exponentiated. For example, the subject invention can be used for exponentiation of number as large as 21024, 22048, 24096, or even larger.