公开(公告)号：US20200174790A1

公开(公告)日：2020-06-04

申请号：US16616385

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Mikhail PLOTNIKOV ,  Christopher J. HUGHES ,  Andrey NARAIKIN

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to a new instruction for detecting conflicts in a set of vector elements and determining a number of instances of each distinct data value within the vector. A system includes circuits to fetch, decode, and execute an instruction that includes an opcode, a destination vector identifier, a source vector identifier, and an immediate value, wherein the execution circuit is to, for each data element position of a source vector, determine a number of matching data element positions in the source vector storing a same data value as stored at the data element position, the matching data element positions located between the data element position and a least significant data element position of the source vector, and store in a corresponding data element position of a destination vector identified by the destination vector identifier, a value representing the number of matching data element positions.

公开(公告)号：US20190121642A1

公开(公告)日：2019-04-25

申请号：US16228462

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Mikhail PLOTNIKOV ,  Andrey NARAIKIN ,  Robert VALENTINE

IPC: G06F9/30 ,  G06F9/38

Abstract: Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

公开(公告)号：US20210294605A1

公开(公告)日：2021-09-23

申请号：US16616379

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Mikhail PLOTNIKOV ,  Christopher J. HUGHES ,  Andrey NARAIKIN

IPC: G06F9/30

Abstract: Disclosed embodiments relate to a new instruction for detecting conflicts in a set of vector elements. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, a destination vector identifier, and a source vector identifier, wherein the execution circuit is to, for each data element position of a source vector identified by the source vector identifier, determine a nearest matching data element position in the source vector storing a same data value as stored at the data element position, the nearest matching data element position located between the data element position and a least significant data element position of the source vector, and store, in a corresponding data element position of a destination vector identified by the destination vector identifier, a value identifying the determined nearest data element position.

公开(公告)号：US20190121643A1

公开(公告)日：2019-04-25

申请号：US16228529

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Mikhail PLOTNIKOV ,  Andrey NARAIKIN ,  Robert VALENTINE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3834

Abstract: Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.