公开(公告)号：US10402413B2

公开(公告)日：2019-09-03

申请号：US15475238

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Mahesh Mamidipaka ,  Srivatsava Jandhyala ,  Anish N K ,  Nagadastagiri Reddy C ,  Sreenivas Subramoney

IPC: G06F17/30 ,  G06F16/2457 ,  G06F16/248 ,  G06F16/9535 ,  G06F16/2455

Abstract: A processor may include a plurality of processing elements and a hardware accelerator for selecting data elements. The hardware accelerator may: access an input data set comprising a set of data elements, each data element having a score value; increment bin counters based on the score values of the set of data elements, each bin counter to count a number of data elements with an associated score value; determine a cumulative sum of count values for a sequence of bin counters, the sequence beginning with a first bin counter of the plurality of bin counters; identify a second bin counter in the sequence of bin counters at which the cumulative sum reaches a selection quantity N; and generate an output data set based on a comparison of the set of data elements to a threshold score associated with the second bin counter.

公开(公告)号：US10540420B2

公开(公告)日：2020-01-21

申请号：US15858788

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Gurpreet Singh Kalsi ,  Om Ji Omer ,  Santhosh Kumar Rethinagiri ,  Anish N K ,  Dipan Kumar Mandal

IPC: G06F17/16 ,  G06F7/544

Abstract: Systems and methods for a hardware accelerated matrix decomposition matrix decomposition circuit are described herein. This matrix decomposition circuit splits matrix decomposition operations into parallel operation circuits and serial operation circuits, and joins the parallel and serial operation circuits using specific dependency handling logic for efficient parallel execution. This provides fast matrix decomposition with low power consumption, reduced memory footprint, and reduced memory bandwidth.