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公开(公告)号：US10540420B2
公开(公告)日：2020-01-21
申请号：US15858788
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Gurpreet Singh Kalsi , Om Ji Omer , Santhosh Kumar Rethinagiri , Anish N K , Dipan Kumar Mandal
Abstract: Systems and methods for a hardware accelerated matrix decomposition matrix decomposition circuit are described herein. This matrix decomposition circuit splits matrix decomposition operations into parallel operation circuits and serial operation circuits, and joins the parallel and serial operation circuits using specific dependency handling logic for efficient parallel execution. This provides fast matrix decomposition with low power consumption, reduced memory footprint, and reduced memory bandwidth.
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