EFFICIENCY ENHANCED CIRCUIT DIGITAL-TO-ANALOG CONVERTER (CDAC) BY OPTIMIZED Q OF THE OFF-LOAD CAP

    公开(公告)号:US20220407529A1

    公开(公告)日:2022-12-22

    申请号:US17763224

    申请日:2019-12-26

    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. A number of capacitive digital analog converter (CDAC) cells of a power amplifier can be sized to provide defined power signals along a signal path. In response to an optimization component that is coupled to a CDAC cell of the plurality of CDAC cells operating in a high efficiency enable mode and the CDAC cell being powered off in an off mode, the optimization component can increase a power efficiency of the power amplifier by reducing an impedance of an output capacitor of the CDAC cell.

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