公开(公告)号：US12119344B2

公开(公告)日：2024-10-15

申请号：US17033440

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Anthony V. Mule' ,  David J. Towner ,  Dragos Seghete ,  Christopher R. Ryder ,  Angel Aquino Gonzalez

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/41791 ,  H01L29/785

Abstract: Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line.