公开(公告)号：US20190294559A1

公开(公告)日：2019-09-26

申请号：US15934916

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： VEDVYAS SHANBHOGUE ,  JOSEPH NUZMAN ,  BAIJU PATEL

IPC: G06F12/14 ,  G06F21/52 ,  G06F12/02

Abstract: Systems, methods, and apparatuses for defending against cross-privilege linear access are described. For example, an implementation of an apparatus comprising privilege level storage to store a current privilege level and address check circuitry coupled to the privilege level storage, wherein the address check circuitry is to determine whether a linear address associated with an instruction is allowed to access a partition of a linear address space of the apparatus based upon a comparison of the current privilege level and a most significant bit of the linear address is described.

公开(公告)号：US20220417005A1

公开(公告)日：2022-12-29

申请号：US17358952

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： BAIJU PATEL ,  SIDDHARTHA CHHABRA ,  PRASHANT DEWAN ,  OFIR SHWARTZ

IPC: H04L9/08

Abstract: Systems, methods, and apparatuses for providing chiplet binding to a disaggregated architecture for a system on a chip are described. In one embodiment, system includes a plurality of physically separate dies, an interconnect to electrically couple the plurality of physically separate dies together, a first die-to-die communication circuit, of a first die of the plurality of physically separate dies, comprising a transmitter circuit and an encryption circuit having a link key to encrypt data to be sent from the transmitter circuit into encrypted data, and a second die-to-die communication circuit, of a second die of the plurality of physically separate dies, comprising a receiver circuit and a decryption circuit having the link key to decrypt the encrypted data sent from the transmitter circuit to the receiver circuit.