公开(公告)号：US20150287779A1

公开(公告)日：2015-10-08

申请号：US14726282

申请日：2015-05-29

Applicant: Intel Corporation

Inventor： Ritesh Jhaveri ,  Bernard SELL ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.

Abstract translation: 在高鳍的顶表面上形成硬掩模蚀刻停止件以保持翅片高度，并且在晶体管制造工艺的蚀刻步骤期间保护翅片的顶表面免受损坏。 在一个实施例中，使用双硬掩模系统形成硬掩模蚀刻停止件，其中在衬底的表面上形成硬掩模蚀刻停止层，并且使用第二硬掩模层来用硬掩模 在鳍的顶表面上的蚀刻停止层。 去除第二硬掩模层，同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。