公开(公告)号：US10534710B2

公开(公告)日：2020-01-14

申请号：US16015880

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F12/0897 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/126 ,  G06F12/0868 ,  G06F12/0873

Abstract: In embodiments, an apparatus may include a CC, and a LLC coupled to the CC, the CC to reserve a defined portion of the LLC where data objects whose home location is in a NVM are given placement priority. In embodiments, the apparatus may be further coupled to at least one lower level cache and a second LLC, wherein the CC may further identify modified data objects in the at least one lower level cache whose home location is in a second NVM, and in response to the identification, cause the modified data objects to be written from the lower level cache to the second LLC, the second LLC located in a same socket as the second NVM.

公开(公告)号：US20190384707A1

公开(公告)日：2019-12-19

申请号：US16006956

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F12/0804 ,  G06F3/06

Abstract: In one embodiment, a processor has a core including at least one execution circuit, a retirement circuit, a first cache memory, and a first cache controller to control the first cache memory, where the first cache controller, in response to a store request to store a first value to a memory coupled to the processor, is to suppress the store operation when the first value matches a stored value of a cache line associated with the store operation. Other embodiments are described and claimed.

公开(公告)号：US20190042457A1

公开(公告)日：2019-02-07

申请号：US16109228

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Bhanu Shankar ,  Vineet Singh

IPC: G06F12/0893

Abstract: Apparatuses, methods and storage medium associated with workload working set size determination, are disclosed herein. In embodiments, at least one computer-readable storage medium includes instructions stored therein to cause an apparatus to intermittently sample memory access operations associated with execution of a workload; generate a trace of memory addresses of the memory access operations sampled; generate a profile of average memory footprints for various trace window sizes; and generate a profile of cache miss rate. The profile of cache miss rate is used to determine a working set size of the workload. Other embodiments are also described and claimed.

公开(公告)号：US20190042416A1

公开(公告)日：2019-02-07

申请号：US16015880

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F12/0804

Abstract: In embodiments, an apparatus may include a CC, and a LLC coupled to the CC, the CC to reserve a defined portion of the LLC where data objects whose home location is in a NVM are given placement priority. In embodiments, the apparatus may be further coupled to at least one lower level cache and a second LLC, wherein the CC may further identify modified data objects in the at least one lower level cache whose home location is in a second NVM, and in response to the identification, cause the modified data objects to be written from the lower level cache to the second LLC, the second LLC located in a same socket as the second NVM.

公开(公告)号：US10795585B2

公开(公告)日：2020-10-06

申请号：US16015517

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F3/06 ,  G06F12/08

Abstract: An embodiment of a semiconductor apparatus may include technology to determine if a memory operation on a memory is avoidable, and suppress the memory operation if the memory operation is determined to be avoidable. Other embodiments are disclosed and claimed.

公开(公告)号：US10528470B1

公开(公告)日：2020-01-07

申请号：US16006956

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F12/00 ,  G06F12/0804 ,  G06F3/06

Abstract: In one embodiment, a processor has a core including at least one execution circuit, a retirement circuit, a first cache memory, and a first cache controller to control the first cache memory, where the first cache controller, in response to a store request to store a first value to a memory coupled to the processor, is to suppress the store operation when the first value matches a stored value of a cache line associated with the store operation. Other embodiments are described and claimed.

公开(公告)号：US10496536B2

公开(公告)日：2019-12-03

申请号：US16015880

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F12/0897 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/126 ,  G06F12/0868 ,  G06F12/0873

Abstract: In embodiments, an apparatus may include a CC, and a LLC coupled to the CC, the CC to reserve a defined portion of the LLC where data objects whose home location is in a NVM are given placement priority. In embodiments, the apparatus may be further coupled to at least one lower level cache and a second LLC, wherein the CC may further identify modified data objects in the at least one lower level cache whose home location is in a second NVM, and in response to the identification, cause the modified data objects to be written from the lower level cache to the second LLC, the second LLC located in a same socket as the second NVM.

公开(公告)号：US20190042108A1

公开(公告)日：2019-02-07

申请号：US16015517

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Bhanu Shankar

IPC: G06F3/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine if a memory operation on a memory is avoidable, and suppress the memory operation if the memory operation is determined to be avoidable. Other embodiments are disclosed and claimed.