公开(公告)号：US11037050B2

公开(公告)日：2021-06-15

申请号：US16458020

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Krishna N. Vinod ,  Sujoyita Kaushikkar ,  Aniket S. Kakade ,  Kermin ChoFleming ,  Ping Zou ,  Alexey Suprun ,  Bhavya K. Daya

IPC: G06N3/04 ,  G06F7/53 ,  G06F1/3234 ,  G06F9/22

Abstract: Systems, methods, and apparatuses relating to arbitration among a plurality of memory interface circuits in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for improved memory sub-system design via arbitration and the improvements to arbitration discussed herein.