公开(公告)号：US10853073B2

公开(公告)日：2020-12-01

申请号：US16024849

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming, Jr. ,  Ping Zou ,  Mitchell Diamond ,  Benjamin Keen

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/50 ,  G06F15/82 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to conditional operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes an output buffer of a first processing element coupled to an input buffer of a second processing element via a first data path that is to send a first dataflow token from the output buffer of the first processing element to the input buffer of the second processing element when the first dataflow token is received in the output buffer of the first processing element; an output buffer of a third processing element coupled to the input buffer of the second processing element via a second data path that is to send a second dataflow token from the output buffer of the third processing element to the input buffer of the second processing element when the second dataflow token is received in the output buffer of the third processing element; a first backpressure path from the input buffer of the second processing element to the first processing element to indicate to the first processing element when storage is not available in the input buffer of the second processing element; a second backpressure path from the input buffer of the second processing element to the third processing element to indicate to the third processing element when storage is not available in the input buffer of the second processing element; and a scheduler of the second processing element to cause storage of the first dataflow token from the first data path into the input buffer of the second processing element when both the first backpressure path indicates storage is available in the input buffer of the second processing element and a conditional token received in a conditional queue of the second processing element from another processing element is a first value.

公开(公告)号：US11037050B2

公开(公告)日：2021-06-15

申请号：US16458020

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Krishna N. Vinod ,  Sujoyita Kaushikkar ,  Aniket S. Kakade ,  Kermin ChoFleming ,  Ping Zou ,  Alexey Suprun ,  Bhavya K. Daya

IPC: G06N3/04 ,  G06F7/53 ,  G06F1/3234 ,  G06F9/22

Abstract: Systems, methods, and apparatuses relating to arbitration among a plurality of memory interface circuits in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for improved memory sub-system design via arbitration and the improvements to arbitration discussed herein.

公开(公告)号：US10564980B2

公开(公告)日：2020-02-18

申请号：US15944761

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Kermin E. Fleming, Jr. ,  Ping Zou ,  Mitchell Diamond ,  Benjamin Keen

IPC: G06F9/38 ,  G06F13/40 ,  G06F15/80 ,  G06F9/448

Abstract: Systems, methods, and apparatuses relating to conditional queues in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first output buffer of a first processing element coupled to a first input buffer of a second processing element and a second input buffer of a third processing element via a data path that is to send a dataflow token to the first input buffer of the second processing element and the second input buffer of the third processing element when the dataflow token is received in the first output buffer of the first processing element; a first backpressure path from the first input buffer of the second processing element to the first processing element to indicate to the first processing element when storage is not available in the first input buffer of the second processing element; a second backpressure path from the second input buffer of the third processing element to the first processing element to indicate to the first processing element when storage is not available in the second input buffer of the third processing element; and a scheduler of the second processing element to cause storage of the dataflow token from the data path into the first input buffer of the second processing element when both the first backpressure path indicates storage is available in the first input buffer of the second processing element and a conditional token received in a conditional queue of the second processing element from another processing element is a true conditional token.

公开(公告)号：US10459866B1

公开(公告)日：2019-10-29

申请号：US16024801

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming, Jr. ,  Mitchell Diamond ,  Ping Zou ,  Benjamin Keen

IPC: G06F9/00 ,  G06F13/40 ,  G06F13/16

Abstract: Systems, methods, and apparatuses relating to integrated control and data processing in a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; a network between the plurality of processing elements to transfer values between the plurality of processing elements; and a first processing element of the plurality of processing elements including a first plurality of input queues having a first width coupled to the network, a second plurality of input queues having a second, larger width coupled to the network, at least one first output queue having the first width coupled to the network, at least one second output queue having the second, larger width coupled to the network, a first operation circuitry coupled to the first plurality of input queues having the first width, a second operation circuitry coupled to the second plurality of input queues having the second, larger width, and a configuration register within the first processing element to store a configuration value that causes the first operation circuitry to perform a second operation on values from the first plurality of input queues to create a first resultant value, and when the first resultant value is a first value, the second operation circuitry is to perform a third operation on values from the second plurality of input queues to create a second resultant value and store the second resultant value in the at least one second output queue.

公开(公告)号：US20190303168A1

公开(公告)日：2019-10-03

申请号：US15944761

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Kermin E. Fleming, JR. ,  Ping Zou ,  Mitchell Diamond ,  Benjamin Keen

IPC: G06F9/38 ,  G06F9/448 ,  G06F15/80 ,  G06F13/40

Abstract: Systems, methods, and apparatuses relating to conditional queues in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first output buffer of a first processing element coupled to a first input buffer of a second processing element and a second input buffer of a third processing element via a data path that is to send a dataflow token to the first input buffer of the second processing element and the second input buffer of the third processing element when the dataflow token is received in the first output buffer of the first processing element; a first backpressure path from the first input buffer of the second processing element to the first processing element to indicate to the first processing element when storage is not available in the first input buffer of the second processing element; a second backpressure path from the second input buffer of the third processing element to the first processing element to indicate to the first processing element when storage is not available in the second input buffer of the third processing element; and a scheduler of the second processing element to cause storage of the dataflow token from the data path into the first input buffer of the second processing element when both the first backpressure path indicates storage is available in the first input buffer of the second processing element and a conditional token received in a conditional queue of the second processing element from another processing element is a true conditional token.

公开(公告)号：US20220405209A1

公开(公告)日：2022-12-22

申请号：US17352628

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Kermin ChoFleming ,  Yu Bai ,  Ping Zou

IPC: G06F12/0895 ,  G06F12/0853 ,  G06F12/0811 ,  G06F12/02

Abstract: An embodiment of an integrated circuit comprises circuitry to generate a cache tag for data to be stored in a cache memory, store a first portion of the cache tag in a primary tag memory, and store a second portion of the cache tag in a secondary tag memory, wherein a size of the first portion is smaller than a size of the second portion. Other embodiments are disclosed and claimed.

公开(公告)号：US10565134B2

公开(公告)日：2020-02-18

申请号：US15859473

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming, Jr. ,  Ping Zou ,  Mitchell Diamond

IPC: G06F13/16

Abstract: Systems, methods, and apparatuses relating to multicast in a configurable spatial accelerator are described. In one embodiment, an accelerator includes a first output buffer of a first processing element coupled to a first input buffer of a second processing element and a second input buffer of a third processing element; and the first processing element determines that it was able to complete a transmission in a previous cycle when the first processing element observed for both the second processing element and the third processing element that either a speculation value was set to a value to indicate a dataflow token was stored in its input buffer (e.g., as indicated by a reception value (e.g., bit)) or a backpressure value was set to a value to indicate that storage is to be available in its input buffer before dequeuing the dataflow token from the first output buffer.

公开(公告)号：US20190205269A1

公开(公告)日：2019-07-04

申请号：US15859473

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Kermin E. Fleming, JR. ,  Ping Zou ,  Mitchell Diamond

IPC: G06F13/16

Abstract: Systems, methods, and apparatuses relating to multicast in a configurable spatial accelerator are described. In one embodiment, an accelerator includes a first output buffer of a first processing element coupled to a first input buffer of a second processing element and a second input buffer of a third processing element; and the first processing element determines that it was able to complete a transmission in a previous cycle when the first processing element observed for both the second processing element and the third processing element that either a speculation value was set to a value to indicate a dataflow token was stored in its input buffer (e.g., as indicated by a reception value (e.g., bit)) or a backpressure value was set to a value to indicate that storage is to be available in its input buffer before dequeuing the dataflow token from the first output buffer.