公开(公告)号：US20170286298A1

公开(公告)日：2017-10-05

申请号：US15085599

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Vedaraman GEETHA ,  Brian S. MORRIS ,  Binata BHATTACHARYYA ,  Massimo SUTERA

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F2212/283 ,  G06F2212/621

Abstract: Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory includes a near memory cache. The computing system directs system memory access requests whose addresses map to a same near memory cache slot to a same home caching agent so that the same home caching agent can characterize individual cache lines as inclusive or non-inclusive before forwarding the requests to a system memory controller, and where the computing system directs other system memory access requests to the system memory controller without passing the other requests through a home caching agent. The electronic circuitry is to modify the respective original addresses of the other requests to include a special code that causes the other system memory access requests to map to a specific pre-determined set of slots within the near memory cache.