公开(公告)号：US20180004433A1

公开(公告)日：2018-01-04

申请号：US15684936

申请日：2017-08-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman GEETHA ,  Henk G. NEEFS ,  Brian S. MORRIS ,  Sreenivas MANDAVA ,  Massimo SUTERA

IPC: G06F3/06 ,  G06F12/0893 ,  G06F12/0866

CPC classification number: G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US20210263993A1

公开(公告)日：2021-08-26

申请号：US17256195

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Maciej URBANSKI ,  Brian J. HICKMANN ,  Michael ROTZIN ,  Krishnakumar NAIR ,  Andrew YANG ,  Brian S. MORRIS ,  Dennis BRADFORD

IPC: G06F17/16 ,  G06F7/523

Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. In one embodiment, a combined fixed-point and floating-point vector multiplication circuit includes at least one switch to change the circuit between a first mode and a second mode, where in the first mode, each multiplier of a set of multipliers is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a corresponding product, shift the corresponding products with a set of shift registers based on a maximum exponent of exponents for the corresponding products determined by a maximum exponent determiner to produce shifted products, perform an numeric conversion operation on the shifted products with a set of numeric conversion circuits based on sign bits from the same element position of the first floating-point vector and the second floating-point vector to produce signed representations of the shifted products, add the signed representations of the shifted products with a set of adders to produce a single product, and normalize the single product with a normalization circuit based on the maximum exponent into a single floating-point resultant, and in the second mode, each multiplier of the set of multipliers is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, and add each corresponding product with the set of adders to produce a single integer resultant.

公开(公告)号：US20180196709A1

公开(公告)日：2018-07-12

申请号：US15912450

申请日：2018-03-05

Applicant: INTEL CORPORATION

Inventor： Debaleena DAS ,  Rajat AGARWAL ,  Brian S. MORRIS

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1064

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

公开(公告)号：US20170286298A1

公开(公告)日：2017-10-05

申请号：US15085599

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Vedaraman GEETHA ,  Brian S. MORRIS ,  Binata BHATTACHARYYA ,  Massimo SUTERA

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F2212/283 ,  G06F2212/621

Abstract: Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory includes a near memory cache. The computing system directs system memory access requests whose addresses map to a same near memory cache slot to a same home caching agent so that the same home caching agent can characterize individual cache lines as inclusive or non-inclusive before forwarding the requests to a system memory controller, and where the computing system directs other system memory access requests to the system memory controller without passing the other requests through a home caching agent. The electronic circuitry is to modify the respective original addresses of the other requests to include a special code that causes the other system memory access requests to map to a specific pre-determined set of slots within the near memory cache.