公开(公告)号：US20190391868A1

公开(公告)日：2019-12-26

申请号：US16556565

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Bradley T. Coffman ,  Gustavo P. Espinosa ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/07 ,  G06F11/30 ,  G05F1/575 ,  G05F1/56 ,  G06F1/30

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

公开(公告)号：US20230385144A1

公开(公告)日：2023-11-30

申请号：US18302999

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Bradley T. Coffman ,  Gustavo P. Espinosa ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/07 ,  G05F1/56 ,  G06F11/30 ,  G05F1/575 ,  G06F1/30

CPC classification number: G06F11/0793 ,  G05F1/562 ,  G06F11/3058 ,  G05F1/575 ,  G06F1/30

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

公开(公告)号：US12164370B2

公开(公告)日：2024-12-10

申请号：US18302999

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Bradley T. Coffman ,  Gustavo P. Espinosa ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/00 ,  G05F1/56 ,  G05F1/575 ,  G06F1/30 ,  G06F11/07 ,  G06F11/30

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

公开(公告)号：US11669385B2

公开(公告)日：2023-06-06

申请号：US16556565

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Bradley T. Coffman ,  Gustavo P. Espinosa ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F1/30 ,  G05F1/56 ,  G05F1/575

CPC classification number: G06F11/0793 ,  G05F1/562 ,  G05F1/575 ,  G06F1/30 ,  G06F11/3058

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.