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公开(公告)号：US20240420274A1
公开(公告)日：2024-12-19
申请号：US18336821
申请日：2023-06-16
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , James Valerio
IPC: G06T1/20
Abstract: Described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. The performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. In one embodiment, performance monitoring for the separate workloads can be configured, for example, by filtering based on the respective shader programs, fixed function units, and/or processing resources used to execute the workloads.
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公开(公告)号：US10749547B2
公开(公告)日：2020-08-18
申请号：US15938505
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr , Gustavo P. Espinosa , Daren J. Schmidt
Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.
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公开(公告)号：US20190391868A1
公开(公告)日：2019-12-26
申请号：US16556565
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Bradley T. Coffman , Gustavo P. Espinosa , Ivan Rodrigo Herrera Mejia
Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.
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公开(公告)号：US10678623B2
公开(公告)日：2020-06-09
申请号：US15818429
申请日：2017-11-20
Applicant: Intel Corporation
Inventor： Michael N. Derr , Balaji Vembu , Michael Mishaeli , Brent Chartrand , Bryan R White , Gustavo Espinosa , Prashant D. Chaudhari
Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.
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公开(公告)号：US20190051266A1
公开(公告)日：2019-02-14
申请号：US16139188
申请日：2018-09-24
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr
Abstract: Technologies for end-to-end display integrity verification include a computing device with a display controller coupled to a display by a physical link. The computing device generates pixel data in a data buffer in memory, and the display controller outputs a pixel signal on the physical link based on the pixel data using a physical interface. The display receives the pixel signal and displays a corresponding image. A splicer is connected to the physical link and repeats the pixel signal to an I/O port of the computing device. The I/O port may be a USB Type-C port. The computing device compares pixel data received by the I/O port to the pixel data in the data buffer. The computing device may calculate checksums of the pixel data. If the pixel data does not match, the computing device may indicate a display integrity failure. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20190050279A1
公开(公告)日：2019-02-14
申请号：US15818429
申请日：2017-11-20
Applicant: Intel Corporation
Inventor： Michael N. Derr , Balaji Vembu , Michael Mishaeli , Brent Chartrand , Bryan R. White , Gustavo Espinosa , Prashant D. Chaudhari
IPC: G06F11/07
Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.
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公开(公告)号：US20230385144A1
公开(公告)日：2023-11-30
申请号：US18302999
申请日：2023-04-19
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Bradley T. Coffman , Gustavo P. Espinosa , Ivan Rodrigo Herrera Mejia
CPC classification number: G06F11/0793 , G05F1/562 , G06F11/3058 , G05F1/575 , G06F1/30
Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.
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公开(公告)号：US11544160B2
公开(公告)日：2023-01-03
申请号：US16456403
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr , Bradley Coffman , Arthur Jeremy Runyan , Gustavo Patricio Espinosa , Daniel James Knollmueller , Ivan Rodrigo Herrera Mejia
Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.
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公开(公告)号：US10387993B2
公开(公告)日：2019-08-20
申请号：US15721273
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr , Arthur J. Runyan
Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.
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10.发明申请公开(公告)号：US20240419447A1
公开(公告)日：2024-12-19
申请号：US18336826
申请日：2023-06-16
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Kevin Hurd
Abstract: Described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. The performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. In one embodiment, performance monitoring for the separate workloads can be configured, for example, by filtering based on the respective contexts used to execute the workloads, the specific instructions executed respectively by the workloads, or the datatypes used respectively by the workloads.
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