公开(公告)号：US20240152373A1

公开(公告)日：2024-05-09

申请号：US17983425

申请日：2022-11-09

Applicant: Intel Corporation

Inventor： Raoul Rivas Toledano ,  Brandon Luk ,  William Braun

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: In one embodiment, a method includes: receiving, in a first circuit of a processor, an indication of an entry of the processor into a first virtual machine, the processor to execute in a virtual machine environment having a root partition and at least one virtual partition comprising the first virtual machine; allocating a first hardware feedback structure for the root partition and allocating a second hardware feedback structure for the at least one virtual partition; populating the first hardware feedback structure with first performance and efficiency information regarding a plurality of cores of the processor; populating the second hardware feedback structure with the first performance and efficiency information regarding the plurality of cores of the processor; and providing the first performance and efficiency information from the second hardware feedback structure to a virtual machine scheduler of the at least one virtual partition. Other embodiments are described and claimed.