公开(公告)号：US20170300326A1

公开(公告)日：2017-10-19

申请号：US15438712

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  SULEYMAN SAIR ,  KSHITIJ A. DOSHI ,  CHARLES R. YOUNT ,  BRET L. TOLL

IPC: G06F9/30 ,  H03M7/46

CPC classification number: G06F9/30018 ,  G06F9/30036 ,  H03M7/46

Abstract: A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.