公开(公告)号：US20160378467A1

公开(公告)日：2016-12-29

申请号：US14751892

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： KSHITIJ A. DOSHI

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/30098 ,  G06F11/00 ,  G06F11/1407 ,  G06F12/0875 ,  G06F2212/452

Abstract: A processor includes at least one memory controller, and a decode unit to decode a persistent commit demarcate instruction. The persistent commit demarcate instruction is to indicate a destination storage location. The processor also includes an execution unit coupled with the decode unit and the at least one memory controller. The execution unit, in response to the persistent commit demarcate instruction, is to store a demarcation value in the destination storage location. The demarcation value may demarcate at least all first store to persistent memory operations that are to have been accepted to memory when the persistent commit demarcate instruction is performed, but which are not necessarily to have been stored persistently, from at least all second store to persistent memory operations that are not yet to have been accepted to memory when the persistent commit demarcate instruction is performed.

Abstract translation: 处理器包括至少一个存储器控制器和解码单元，用于解码持久性提交分界指令。 持久的提交分界指令是指示目的地存储位置。 处理器还包括与解码单元和至少一个存储器控制器耦合的执行单元。 执行单元响应于持续提交分界符指令，将目标存储位置中的分界值存储。 当执行持久性提交分界指令时，分界值至少可以将所有第一存储区域划分为将被接受到存储器的持久存储器操作，但是不一定必须从至少所有第二存储区段持续存储到持久存储器操作 当执行持久性提交分界符指令时，尚未被内存接受的内存操作。

公开(公告)号：US20220200872A1

公开(公告)日：2022-06-23

申请号：US17690642

申请日：2022-03-09

Applicant: INTEL CORPORATION

Inventor： FRANCESC GUIM BERNAT ,  KSHITIJ A. DOSHI ,  DANIEL RIVAS BARRAGAN ,  MARK A. SCHMISSEUR ,  STEEN LARSEN

IPC: H04L41/5025 ,  H04L43/0817 ,  H04L43/16 ,  H04L41/0896

Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.

公开(公告)号：US20170300326A1

公开(公告)日：2017-10-19

申请号：US15438712

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  SULEYMAN SAIR ,  KSHITIJ A. DOSHI ,  CHARLES R. YOUNT ,  BRET L. TOLL

IPC: G06F9/30 ,  H03M7/46

CPC classification number: G06F9/30018 ,  G06F9/30036 ,  H03M7/46

Abstract: A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.

公开(公告)号：US20240179078A1

公开(公告)日：2024-05-30

申请号：US18526782

申请日：2023-12-01

Applicant: INTEL CORPORATION

Inventor： FRANCESC GUIM BERNAT ,  KSHITIJ A. DOSHI ,  DANIEL RIVAS BARRAGAN ,  MARK A. SCHMISSEUR ,  STEEN LARSEN

IPC: H04L41/5025 ,  H04L41/0896 ,  H04L43/0817 ,  H04L43/16

CPC classification number: H04L41/5025 ,  H04L41/0896 ,  H04L43/0817 ,  H04L43/16

Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.

公开(公告)号：US20210273863A1

公开(公告)日：2021-09-02

申请号：US17202703

申请日：2021-03-16

Applicant: INTEL CORPORATION

Inventor： FRANCESC GUIM BERNAT ,  KSHITIJ A. DOSHI ,  DANIEL RIVAS BARRAGAN ,  MARK A. SCHMISSEUR ,  STEEN LARSEN

IPC: H04L12/24 ,  H04L12/26

Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.

公开(公告)号：US20190004851A1

公开(公告)日：2019-01-03

申请号：US15637476

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： KSHITIJ A. DOSHI ,  VADIM SUKHOMLINOV ,  ROMAN DEMENTIEV

IPC: G06F9/46 ,  G06F12/0831 ,  G06F9/30

Abstract: A method to perform atomic transactions in non-volatile memory (NVM) under hardware transactional memory is disclosed. The method includes tracking an order among transaction log entries that includes arranging transaction logs in an order that is based on when corresponding transactions were executed. Moreover, the method includes, using the ordered transaction logs to recover data states of the nonvolatile memory, by identifying a first unconfirmed transaction associated with a transaction completion uncertainty event based on a corresponding one of the transaction logs including a first commit marker but not including a confirm marker, undoing first ones of the transactions in reverse time order starting at a last transaction that recorded a second commit marker, up to and including the first unconfirmed transaction that recorded the first commit marker, and redoing second ones of the transactions in forward time order from a first confirmed transaction up to but not including the first unconfirmed transaction that recorded the first commit marker.

公开(公告)号：US20180091383A1

公开(公告)日：2018-03-29

申请号：US15279375

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： FRANCESC GUIM BERNAT ,  KSHITIJ A. DOSHI ,  DANIEL RIVAS BARRAGAN ,  MARK A. SCHMISSEUR ,  STEEN LARSEN

IPC: H04L12/24 ,  H04L12/26

CPC classification number: H04L41/5025 ,  H04L41/0896 ,  H04L43/0817 ,  H04L43/16

Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.

公开(公告)号：US20170185354A1

公开(公告)日：2017-06-29

申请号：US14757603

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： KSHITIJ A. DOSHI ,  SANJEEV N. TRIKA ,  SRIDHARAN SAKTHIVELU

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0685 ,  G06F9/466 ,  G06F12/1027 ,  G06F13/00

Abstract: Examples include techniques for a write transaction to one or more memory devices maintained at a storage device. In some examples, the write transaction includes a disjointed atomic write transaction that includes a plurality of asynchronous write operations from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the disjointed atomic write transaction is associated with a multi-block transaction request initiated by the application or operating system that upon acceptance results in the plurality of asynchronous write operations to the storage device.