公开(公告)号：US20220206793A1

公开(公告)日：2022-06-30

申请号：US17134154

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： WING SHEK WONG ,  VIKASH AGARWAL ,  CHARLES VITU ,  MADHURA SARODE

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to a scalable reservation station circuit implementing a single unified speculation state propagation and execution wakeup matrix in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode one or more instructions into a first micro-operation to load data from a data cache, a second micro-operation dependent on the first micro-operation, and a third micro-operation dependent on the second micro-operation; an execution circuit to execute the first micro-operation, the second micro-operation, and the third micro-operation; and a reservation station circuit comprising a load speculation tracker circuit and coupled between the decoder circuit and the execution circuit, the load speculation tracker circuit to, for a reservation station entry of the third micro-operation, track progress of the first micro-operation in the data cache to generate a cancellation indication for the third micro-operation in response to a miss of the data in the data cache for the first micro-operation, wherein the load speculation tracker circuit is to begin to track the progress of the first micro-operation in the data cache in response to a dispatch of the first micro-operation into the data cache.

公开(公告)号：US20220206792A1

公开(公告)日：2022-06-30

申请号：US17134108

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： WING SHEK WONG ,  VIKASH AGARWAL ,  CHARLES VITU ,  MIHIR SHAH

IPC: G06F9/22 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic two-pass execution of a partial flag updating instruction in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into a set of one or more micro-operations, an execution circuit to execute the micro-operations decoded for the instructions, a data register to store data, a flag register to store a plurality of flags, and a reservation station circuit coupled between the decoder circuit and the execution circuit, the reservation station circuit to, in response to an indicator bit set to a multiple pass mode for a single micro-operation in a reservation station entry, perform a first dispatch of the single micro-operation to the execution circuit, when a source data operand in the data register is ready for execution and a source flag operand in the flag register is not ready for execution, to generate a data resultant, and a second dispatch of the single micro-operation to the execution circuit when both the source data operand in the data register and the source flag operand in the flag register are ready for execution to generate a flag resultant based on one or more of the plurality of flags in the flag register.