公开(公告)号：US11264449B2

公开(公告)日：2022-03-01

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11901404B2

公开(公告)日：2024-02-13

申请号：US17578043

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/87 ,  H10B12/033 ,  H10B12/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11791375B2

公开(公告)日：2023-10-17

申请号：US17578839

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/87 ,  H10B12/033 ,  H10B12/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.