公开(公告)号：US20200287017A1

公开(公告)日：2020-09-10

申请号：US16294821

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sou-Chi CHANG ,  Chia-Chang LIN ,  Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Nazila HARATIPOURA ,  Owen LOH ,  Jack KAVALIEROS ,  Uygar AVCI ,  Ian YOUNG

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66

Abstract: A gate stack is described that uses anti-ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2) or ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2, perovskite ferroelectric such as NH4H2PO4, KH2PO4, LiNb03, LiTaO3, BaTiO3, PbTiO3, Pb (Zr,Ti) O3, (Pb,La)TiO3, and (Pb,La)(Zr,Ti)O3) which reduces write voltage, improves endurance, and increases retention. The gate stack of comprises strained anti-FE or FE material and depolarized anti-FE or FE. The endurance of the FE transistor is further improved by using a higher K (constant) dielectric (e.g., SiO2, Al2O3, HfO2, Ta2O3, La2O3) in the gate stack. High K effects may also be achieved by depolarizing the FE or FE oxide in the transistor gate stack.