公开(公告)号：US20240211332A1

公开(公告)日：2024-06-27

申请号：US18596471

申请日：2024-03-05

Applicant: Intel Corporation

Inventor： Divya GUPTA ,  Shubhada PUGAONKAR ,  Raed AL-OMARI ,  Mariecel TORRES-YOUNG ,  Ayman G. ABDO ,  John R. AYERS ,  Chih-Cheh CHEN ,  Wilfredo FIGUEROA MARTINEZ ,  Girish CHANDRASEKARAN

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0757 ,  G06F11/0778

Abstract: Examples include techniques to collecting and providing error related information for a multi-die system-on-a-chip (SOC) computing system following a critical or catastrophic error. Examples include circuitry on a first die that is configured to receive an indication of a critical or catastrophic error and cause error related information to be stored to a volatile memory at the first die that is arranged to continually maintain power during a global reset of the SOC. The circuitry can also be configured to provide the stored error related information to a requestor following the global reset of the SOC.