公开(公告)号：US10255196B2

公开(公告)日：2019-04-09

申请号：US14979038

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Christopher Bryant ,  Jeff Wiedemeier

IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/14

Abstract: An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a page walk using a guest physical address (GPA) and to detect whether a page identified with the GPA is mapped with sub-page permissions; a sub-page control storage to store at least one GPA and other data related to a sub-page; the page miss handler to determine whether the GPA is programmed in the sub-page control storage; and the page miss handler to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page control storage when an access matches a TLB entry with sub-page protection indication.

公开(公告)号：US09684605B2

公开(公告)日：2017-06-20

申请号：US14628405

申请日：2015-02-23

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Christopher Bryant

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/30076 ,  G06F12/1009 ,  G06F2212/68

Abstract: Embodiments of an invention for a guest-physical address translation lookaside buffer are disclosed. In an embodiment, a processor includes an instruction decoder, a control register, and memory address translation hardware. The instruction decoder is to receive an instruction to transfer control of the processor to guest software to execute on a virtual machine. The virtual machine is to have a plurality of resources to be controlled by a virtual machine monitor. The virtual machine monitor is to execute on a host machine having a host-physical memory to be accessed using a plurality of host-physical addresses. The plurality of resources is to include a guest-physical memory. The guest software is to access the guest-physical memory using a plurality of guest-virtual addresses. The control register is to store a pointer to a plurality of virtual address page tables. The memory address translation hardware is to translate, without causing a virtual machine exit, guest-virtual addresses to host-physical addresses using the plurality of virtual address page tables and a plurality of extended page tables. The memory address translation hardware includes a virtual address translation lookaside buffer in which to store a plurality of virtual address entries corresponding to guest-virtual address to host-physical address translations. The memory address translation hardware also includes a guest-physical address translation lookaside buffer in which to store a plurality of guest-physical address entries corresponding to guest-physical address to host-physical address translations.