公开(公告)号：US20190227946A1

公开(公告)日：2019-07-25

申请号：US16286361

申请日：2019-02-26

申请人： Cambricon Technologies Corporation Limited

发明人： Tianshi CHEN ,  Qi GUO ,  Yunji CHEN

IPC分类号： G06F12/1027 ,  G06N3/02

CPC分类号： G06F12/1027 ,  G06F2212/68 ,  G06N3/02

摘要： Aspects of managing Translation Lookaside Buffer (TLB) units are described herein. The aspects may include a memory management unit (MMU) that includes one or more TLB units and a control unit. The control unit may be configured to identify one from the one or more TLB units based on a stream identification (ID) included in a received virtual address and, further, to identify a frame number in the identified TLB unit. A physical address may be generated by the control unit based on the frame number and an offset included in the virtual address.

公开(公告)号：US20190155527A1

公开(公告)日：2019-05-23

申请号：US16261046

申请日：2019-01-29

申请人： Red Hat, Inc.

发明人： Michael Tsirkin

IPC分类号： G06F3/06 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/455

CPC分类号： G06F3/0619 ,  G06F3/0631 ,  G06F3/068 ,  G06F9/45558 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/1441 ,  G06F2009/45579 ,  G06F2009/45595 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/657 ,  G06F2212/68

摘要： A device access system includes a memory having a supervisor memory, a processor, an input output memory management unit (IOMMU), and a supervisor. The supervisor includes a supervisor driver, which executes on the processor to allocate the supervisor memory and reserve a range of application virtual addresses. The supervisor driver programs the IOMMU to map the supervisor memory to the reserved range. A device is granted access to the reserved range, which is protected in host page table entries such that an application cannot modify data within the range. The supervisor driver configures the device to use the supervisor memory and receive a request including a virtual address and length from the application to use the device. The supervisor driver validates the request by verifying that the virtual address and length do not overlap the range reserved by the supervisor, and responsive to validating the request, submits the request to the device.

公开(公告)号：US20190012179A1

公开(公告)日：2019-01-10

申请号：US15644670

申请日：2017-07-07

申请人： VMware, Inc.

发明人： Andrei WARKENTIN ,  Cyprien LAPLACE ,  Regis DUCHESNE ,  Alexander FAINKICHEN ,  Ye LI

IPC分类号： G06F9/44 ,  G06F3/06 ,  G06F12/1009 ,  G06F9/38 ,  G06F12/121 ,  G06F12/1027

CPC分类号： G06F9/4403 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/068 ,  G06F9/38 ,  G06F9/4405 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/65 ,  G06F2212/68

摘要： A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.

公开(公告)号：US20180357179A1

公开(公告)日：2018-12-13

申请号：US16005385

申请日：2018-06-11

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC分类号： G06F12/1036 ,  G06F9/455 ,  G06F9/48 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F12/1027

CPC分类号： G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/70

摘要： In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US20180357171A1

公开(公告)日：2018-12-13

申请号：US16103253

申请日：2018-08-14

申请人： International Business Machines Corporation

发明人： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

CPC分类号： G06F12/0831 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/621 ,  G06F2212/68

摘要： A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

公开(公告)号：US20180329637A1

公开(公告)日：2018-11-15

申请号：US16041713

申请日：2018-07-20

申请人： Western Digital Technologies, Inc.

发明人： Ajith Kumar Battaje ,  Tanay Goel ,  Rajendra Prasad Mishra

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/1027

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F12/0246 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/68 ,  G06F2212/702 ,  G06F2212/7201 ,  G06F2212/7205

摘要： A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive in a memory, a first logical block entry for a first dump group and a second logical block entry for a second dump group; store in a reverse translation table, the first logical block entry for the first dump group and the second logical block entry for the second dump group; determine a first sequence number associated with the stored first logical block entry and the stored second logical block entry in the reverse translation table, wherein the first sequence number is a snapshot marker that determines a timestamp associated with the first logical block and the second logical block; and persist the first logical block entry for the first dump group in the storage device.

公开(公告)号：US20180307621A1

公开(公告)日：2018-10-25

申请号：US15493267

申请日：2017-04-21

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Abhishek R. Appu ,  Kiran C. Veernapu

IPC分类号： G06F12/1045 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60

CPC分类号： G06F12/1063 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/455 ,  G06F2212/657 ,  G06F2212/68 ,  G06T1/20 ,  G06T1/60

摘要： One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.

公开(公告)号：US20180293183A1

公开(公告)日：2018-10-11

申请号：US15482690

申请日：2017-04-07

申请人： Intel Corporation

发明人： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F12/1027 ,  G06F12/0802

CPC分类号： G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20180293169A1

公开(公告)日：2018-10-11

申请号：US15483036

申请日：2017-04-10

申请人： ARM Ltd

发明人： Jonathan Curtis BEARD ,  Peter VAN HENSBERGEN

IPC分类号： G06F12/0831 ,  G06F12/1045 ,  G06F12/0875 ,  G06F11/10 ,  G06F13/42

CPC分类号： G06F12/0831 ,  G06F11/1064 ,  G06F12/0813 ,  G06F12/0833 ,  G06F12/0875 ,  G06F12/1054 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/68

摘要： A virtual link buffer provides communication between processing threads or cores. A first cache is accessible by a first processing device and a second cache accessible by a second processing device. An interconnect structure couples between the first and second caches and includes a link controller. A producer cache line in the first cache stores data produced by the first processing device and the link controller transfers data in the producer cache line to a consumer cache line in the second cache. Each new data element is stored at a location in the producer cache line indicated by a store position or tail indicator that is stored at a predetermined location in the same cache line. Transferred data are loaded from a location in the consumer cache line indicated by a load position or head indicator that is stored at a predetermined location in the same consumer cache line.

公开(公告)号：US20180275879A1

公开(公告)日：2018-09-27

申请号：US15994010

申请日：2018-05-31

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Robert Miller, JR. ,  Steven M. Partlow ,  Thomas F. Rankin ,  Scott B. Tuttle ,  Elpida Tzortzatos

IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F12/1027 ,  G06F12/0815 ,  G06F9/46 ,  G06F9/455

CPC分类号： G06F3/0604 ,  G06F3/0608 ,  G06F3/0637 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/08 ,  G06F12/0815 ,  G06F12/1027 ,  G06F2009/45583 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/657 ,  G06F2212/68 ,  H05K999/99

摘要： In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.