公开(公告)号：US11941534B2

公开(公告)日：2024-03-26

申请号：US16729379

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Gurpreet Singh Kalsi ,  Anant V. Nori ,  Christopher Justin Hughes ,  Sreenivas Subramoney ,  Damla Senol

IPC: G06N3/123 ,  G06F9/30 ,  G06F15/78 ,  G06F15/80 ,  G06F40/45 ,  G16B30/00 ,  G16B30/10 ,  G06F17/00

CPC classification number: G06N3/123 ,  G06F9/30036 ,  G06F15/78 ,  G06F15/8053 ,  G06F15/8061 ,  G06F40/45 ,  G16B30/00 ,  G16B30/10 ,  G06F17/00

Abstract: A system is provided that includes a bit vector-based distance counter circuitry configured to generate one or more bit vectors encoded with information about potential matches and edits between a read and a reference genome, wherein the read comprises an encoding of a fragment of deoxyribonucleic acid (DNA) encoded via bases G, A, T, C. The system further includes a bit vector-based traceback circuitry configured to divide the reference genome into one or more windows and to use the plurality of bit vectors to generate a traceback output for each of the one or more windows, wherein the traceback output comprises a match, a substitution, an insert, a delete, or a combination thereof, between the read and the one or more windows.

公开(公告)号：US20210201163A1

公开(公告)日：2021-07-01

申请号：US16729379

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Gurpreet Singh Kalsi ,  Anant V. Nori ,  Christopher Justin Hughes ,  Sreenivas Subramoney ,  Damla Senol

IPC: G06N3/12 ,  G06F15/78 ,  G06F9/30 ,  G16B30/10

Abstract: A system is provided that includes a bit vector-based distance counter circuitry configured to generate one or more bit vectors encoded with information about potential matches and edits between a read and a reference genome, wherein the read comprises an encoding of a fragment of deoxyribonucleic acid (DNA) encoded via bases G, A, T, C. The system further includes a bit vector-based traceback circuitry configured to divide the reference genome into one or more windows and to use the plurality of bit vectors to generate a traceback output for each of the one or more windows, wherein the traceback output comprises a match, a substitution, an insert, a delete, or a combination thereof, between the read and the one or more windows.

公开(公告)号：US20210200711A1

公开(公告)日：2021-07-01

申请号：US16729381

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Kamlesh R. Pillai ,  Gurpreet Singh Kalsi ,  Christopher Justin Hughes

IPC: G06F15/80 ,  G06F17/16 ,  G06F15/78

Abstract: A system is provided that includes a reconfigurable systolic array circuitry. The reconfigurable systolic array circuitry includes a first circuit block comprising one or more groups of processing elements and a second circuit block comprising one or more groups of processing elements. The reconfigurable systolic array circuitry further includes a first bias addition with accumulation circuitry configured to add a matrix bias to an accumulated value, to a multiplication product, or to a combination thereof. The reconfigurable systolic array circuitry additionally includes a first routing circuitry configured to route derivations from the first circuit block into the second circuit block, from the first circuit block into the first bias addition with accumulation circuitry, or into a combination thereof.