公开(公告)号：US10955739B2

公开(公告)日：2021-03-23

申请号：US16647418

申请日：2017-11-28

Applicant: Intel Corporation

Inventor： Harsha Grunes ,  Christopher N. Kenyon ,  Sven Henrichs

IPC: G03F1/36

Abstract: A mask process development having a consistent mask targeting is described. A method includes receiving an integrated circuit (IC) design. A test mask is generated that converts the IC design into one or more physical layouts. A set of one or more sub-resolution assist features (SRAFs) is inserted into the test mask. The set of one or more SRAFs is inserted into one or more other masks, which are derived from the test mask for mask targeting, such that the test mask and the one or more other masks include a same set of the one or more SRAFs.

公开(公告)号：US11043492B2

公开(公告)日：2021-06-22

申请号：US16098084

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Biswajeet Guha ,  Tahir Ghani ,  Christopher N. Kenyon ,  Leonard P. Guler

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

公开(公告)号：US11581315B2

公开(公告)日：2023-02-14

申请号：US17242021

申请日：2021-04-27

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Biswajeet Guha ,  Tahir Ghani ,  Christopher N. Kenyon ,  Leonard P. Guler

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.