公开(公告)号：US11961838B2

公开(公告)日：2024-04-16

申请号：US17736029

申请日：2022-05-03

Applicant: Intel Corporation

Inventor： Byron Ho ,  Chun-Kuo Huang ,  Erica Thompson ,  Jeanne Luce ,  Michael L. Hattendorf ,  Christopher P. Auth ,  Ebony L. Mays

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

公开(公告)号：US10734379B2

公开(公告)日：2020-08-04

申请号：US15859351

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Byron Ho ,  Chun-Kuo Huang ,  Erica Thompson ,  Jeanne Luce ,  Michael L. Hattendorf ,  Christopher P. Auth ,  Ebony L. Mays

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

公开(公告)号：US11380683B2

公开(公告)日：2022-07-05

申请号：US17076425

申请日：2020-10-21

Applicant: Intel Corporation

Inventor： Byron Ho ,  Chun-Kuo Huang ,  Erica Thompson ,  Jeanne Luce ,  Michael L. Hattendorf ,  Christopher P. Auth ,  Ebony L. Mays

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

公开(公告)号：US10861850B2

公开(公告)日：2020-12-08

申请号：US16906680

申请日：2020-06-19

Applicant: Intel Corporation

Inventor： Byron Ho ,  Chun-Kuo Huang ,  Erica Thompson ,  Jeanne Luce ,  Michael L. Hattendorf ,  Christopher P. Auth ,  Ebony L. Mays

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.