公开(公告)号：US20240004662A1

公开(公告)日：2024-01-04

申请号：US17856978

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Amit GRADSTEIN ,  Regev SHEMY ,  Chitra NATARAJAN ,  Leonardo BORGES ,  Chytra SHIVASWAMY ,  Igor ERMOLAEV ,  Michael ESPIG ,  Or BEIT AHARON ,  Jeff WIEDEMEIER

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30025 ,  G06F9/30021

Abstract: Techniques for performing horizontal reductions are described. In some examples, an instance of a horizontal instruction is to include at least one field for an opcode, one or more fields to reference a first source operand, and one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least perform a horizontal reduction using at least one data element of a non-masked data element position of at least the first source operand and store a result of the horizontal reduction in the destination operand.