公开(公告)号：US20240355751A1

公开(公告)日：2024-10-24

申请号：US18136722

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Sanjay THARMARAJAH ,  Hiroki TANAKA ,  Clayton BRENNER

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L21/4846

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a substrate and a pad on the substrate. In an embodiment, a layer is over the pad and the substrate, and an opening through the layer is above the pad. In an embodiment, sidewalls of the layer define the opening. In an embodiment, an undercut at an end of the opening adjacent to the pad is provided, where the undercut is positioned between the pad and the layer. In an embodiment, a bump is in the opening, where the bump at least partially fills the undercut