公开(公告)号：US20240356199A1

公开(公告)日：2024-10-24

申请号：US18762578

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Hsuan Lee ,  Ching-Hua Hsieh ,  Chien-Ling Hwang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC分类号： H01Q1/22 ,  H01L21/48 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/40

CPC分类号： H01Q1/2283 ,  H01L21/4846 ,  H01L23/66 ,  H01L24/13 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01Q1/40 ,  H01L2223/6677 ,  H01L2224/13024 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267

摘要： A method of manufacturing an electronic device includes: providing a composite structure, wherein the composite structure comprises a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer; thinning the two conductive layers to form two thinned conductive layers; forming an antenna pattern using one of the two thinned conductive layers; forming an antenna package to encapsulate the antenna pattern therein; forming a circuit pattern by patterning the other one of the two thinned conductive layers; and forming a chip package to encapsulate the circuit pattern therein, wherein the chip package is electrically coupled to the antenna package.

公开(公告)号：US20240332199A1

公开(公告)日：2024-10-03

申请号：US18226988

申请日：2023-07-27

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Chi Hyeon JEONG ,  Seong Hwan LEE ,  Hyun Sang KWAK ,  Min Cheol PARK ,  Sang Jong LEE

IPC分类号： H01L23/538 ,  H01L21/48

CPC分类号： H01L23/5385 ,  H01L21/4846 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/014

摘要： A printed circuit board includes a substrate having an upper surface at which a plurality of first pads are disposed, and an interconnect structure including an encapsulant, a plurality of second pads disposed at an upper surface of the encapsulant, and a plurality of metal wires disposed in the encapsulant and respectively connected to at least one of the plurality of second pads, the interconnect structure disposed on an upper side of the substrate. At least a portion of an upper surface of each of the plurality of first and second pads is exposed in an upward direction from the upper surface of each of the substrate and the encapsulant.

公开(公告)号：US20240312795A1

公开(公告)日：2024-09-19

申请号：US18604588

申请日：2024-03-14

申请人： Infineon Technologies Austria AG

发明人： Alexander Roth

IPC分类号： H01L21/48 ,  H01L23/14 ,  H01L23/498

CPC分类号： H01L21/4846 ,  H01L23/498 ,  H01L23/142 ,  H01L23/49894

摘要： A semiconductor module includes a first metal layer, a ceramic layer applied on the first metal layer, a second metal layer applied at least in part on the ceramic layer, and a semiconductor die attached on a portion of the second metal layer. A method for fabricating the semiconductor module is also described.

公开(公告)号：US20240266275A1

公开(公告)日：2024-08-08

申请号：US18440381

申请日：2024-02-13

申请人： Liquid Wire Inc.

发明人： Mark William Ronay ,  Trevor Antonio Rivera ,  Michael Adventure Hopkins ,  Edward Martin Godshalk ,  Charles J. Kinzel

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/49838 ,  H01L23/3121 ,  H01L23/4985 ,  H01L23/49861 ,  H01L21/4846

摘要： A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

公开(公告)号：US20240266273A1

公开(公告)日：2024-08-08

申请号：US18418655

申请日：2024-01-22

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Masaya TAKIZAWA ,  Yuki KOBAYASHI

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227

摘要： A wiring board includes an insulating layer covering upper and side surfaces of a first interconnect layer, a via hole penetrating the insulating layer and reaching the first interconnect layer, a second interconnect layer filling the via hole and extending on the insulating layer, and a cavity provided in the first interconnect layer, communicating with the via hole and extending outside than a lower end of an inner side surface of the via hole in a plan view. The second interconnect layer includes a first seed layer provided on the insulating layer, a second seed layer continuously covering upper and inner side surfaces of the first seed layer, the inner side surface of the via hole, and surfaces of the insulating layer and the first interconnect layer exposed inside the cavity, and an electrolytic plating layer provided on the second seed layer thicker than the first seed layer.

公开(公告)号：US20240266239A1

公开(公告)日：2024-08-08

申请号：US18419576

申请日：2024-01-23

申请人： WALTON ADVANCED ENGINEERING, INC.

发明人： HONG-CHI YU ,  CHUN-JUNG LIN ,  RUEI-TING GU

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/82 ,  H01L23/498

CPC分类号： H01L23/3171 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/82 ,  H01L23/498

摘要： A chip package unit with an outer protective layer and a method of manufacturing the same are provided. The chip package unit includes a rectangular die and at least one outer protective layer. The rectangular die has four sides. The outer protective layer is disposed on a surface of the rectangular die and having four sides. The chip package unit is divided from a wafer by a sawing process along cutting channels disposed on the wafer. The outer protective layer is formed on a surface of the wafer and covering the cutting channels completely. A cutting tool is firstly cutting the outer protective layer on the wafer and then moved downward continuously to cut the respective cutting channels. Thus the sides of the outer protective layer are flush with the sides of the rectangular die to avoid damages of the sides of the rectangular die during the sawing process.

公开(公告)号：US20240258243A1

公开(公告)日：2024-08-01

申请号：US18614579

申请日：2024-03-22

申请人： Micron Technology, Inc.

发明人： Jong Sik Paek

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC分类号： H01L23/5386 ,  H01L21/4846 ,  H01L21/566 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48228 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/1436 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/183

摘要： Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.

公开(公告)号：US20240234285A9

公开(公告)日：2024-07-11

申请号：US18217725

申请日：2023-07-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： KEUNYOUNG LEE

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L23/49816

摘要： A semiconductor package includes a substrate. A pattern layer is disposed on a first surface of the substrate. The pattern layer includes a plurality of pads and a plating wire positioned between adjacent pads of the plurality of pads. A first protection layer is disposed on the first surface of the substrate to cover the pattern layer and expose the plurality of pads. At least one pad of the plurality of pads is physically separated from the plating wire.

公开(公告)号：US20240222018A1

公开(公告)日：2024-07-04

申请号：US18147503

申请日：2022-12-28

申请人： Intel Corporation

发明人： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Numair Ahmed ,  Darko Grujicic ,  Suddhasattwa Nad ,  Benjamin Duong ,  Marcel Wall ,  Shayan Kaviani

IPC分类号： H01G4/01 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01G4/01 ,  H01G4/306 ,  H01G4/33 ,  H01L21/4846 ,  H01L23/5386 ,  H01L28/87 ,  H01L28/92 ,  H01G4/008

摘要： Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.

公开(公告)号：US12027470B2

公开(公告)日：2024-07-02

申请号：US17547200

申请日：2021-12-09

申请人： Industrial Technology Research Institute

发明人： Yu-Min Lin ,  Ching-Kuan Lee ,  Chao-Jung Chen ,  Ren-Shin Cheng ,  Ang-Ying Lin ,  Po-Chih Chang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/568 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17

摘要： A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.