公开(公告)号：US20200097291A1

公开(公告)日：2020-03-26

申请号：US16140196

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： CHRISTOPHER J. HUGHES ,  BRET TOLL ,  ALEXANDER HEINECKE ,  DAN BAUM ,  ELMOUSTAPHA OULD-AHMED-VALL ,  RAANAN SADE ,  ROBERT VALENTINE ,  MARK CHARNEY

IPC: G06F9/30 ,  G06F9/48

Abstract: An apparatus and method for tile-based gather and scatter operations. For example, one embodiment of a processor comprises: a destination tile register to store a 2-D arrangement of data elements; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch a tile gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the tile gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register and to load the data elements from the system memory addresses to the destination tile register.

公开(公告)号：US20200272466A1

公开(公告)日：2020-08-27

申请号：US15930887

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： CHRISTOPHER J. HUGHES ,  DAN BAUM

IPC: G06F9/30 ,  G06F15/80 ,  G06F12/0862

Abstract: An apparatus and method for processing efficient multicast operation. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a shared circuitry region to be shared by the plurality of cores; first cache management circuitry associated with the shared circuitry region to receive delayed prefetch messages from the cores, each delayed prefetch message comprising an address or portion thereof usable to identify a cache line; and a delayed prefetch manager comprising a plurality of entries, each entry associated with at least one of the delayed prefetch messages, the delayed prefetch manager to update one or more of the entries or generate a new entry in accordance with receipt of each new delayed prefetch message, wherein upon receiving a notification that a first cache line is being modified by a first core, the delayed prefetch manager is to transmit delayed prefetch response messages to one or more cores identified in a first entry associated with the first cache line.

公开(公告)号：US20190303152A1

公开(公告)日：2019-10-03

申请号：US15941958

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： CHRISTOPHER J. HUGHES ,  DAN BAUM

IPC: G06F9/30 ,  G06F15/80

Abstract: An apparatus and method for processing efficient multicast operation. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a shared circuitry region to be shared by the plurality of cores; first cache management circuitry associated with the shared circuitry region to receive delayed prefetch messages from the cores, each delayed prefetch message comprising an address or portion thereof usable to identify a cache line; and a delayed prefetch manager comprising a plurality of entries, each entry associated with at least one of the delayed prefetch messages, the delayed prefetch manager to update one or more of the entries or generate a new entry in accordance with receipt of each new delayed prefetch message, wherein upon receiving a notification that a first cache line is being modified by a first core, the delayed prefetch manager is to transmit delayed prefetch response messages to one or more cores identified in a first entry associated with the first cache line.